Methodology for optimizing ESD protection for high speed LVDS based I/Os. - Vishnuram Abhinav; Amitabh Chatterjee; Dheeraj Kumar Sinha; Rajan Singh (VDAT, 2015)

A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach. - Vishnuram Abhinav; Dheeraj Kumar Sinha; Amitabh Chatterjee; Forrest Brewer (VLSID, 2016)

A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET. - Dheeraj Kumar Sinha; Amitabh Chatterjee; Vishnuram Abhinav; Gaurav Trivedi; Victor Koldyaev (VLSID, 2016)

Low-Cost, Point-of-Care Potassium Ion Sensing Electrode in EGFET Configuration for Ultra-High Sensitivity. - Vishnuram Abhinav; Tejas R. Naik (IEEE Access, 2024)