Clock Gating and Negative Edge Triggering for Energy Recovery Clock. - Vishwanadh Tirumalashetty; Hamid Mahmoodi (ISCAS, 2007)

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. - Hamid Mahmoodi; Vishy Tirumalashetty; Matthew Cooke; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Deep Researcher with Test-Time Diffusion. - Rujun Han; Yanfei Chen; Zoey CuiZhu; Lesly Miculicich; Guan Sun; Yuanjun Bi; Weiming Wen; Hui Wan; Chunfeng Wen; Solène Maître; George Lee; Vishy Tirumalashetty; et al. (CoRR, 2025)