An Automatic Test Generation System for Illiac IV Logic Boards. - Vishwani D. Agrawal; Prathima Agrawal (IEEE Trans. Computers, 1972)

Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks. - Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Computers, 1975)

On Monte Carlo Testing of Logic Tree Networks. - Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Computers, 1976)

When to Use Random Testing. - Vishwani D. Agrawal (IEEE Trans. Computers, 1978)

Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays". - Vishwani D. Agrawal (IEEE Trans. Computers, 1979)

Author's Reply. - Vishwani D. Agrawal (IEEE Trans. Computers, 1979)

A mixed-mode simulator. - Vishwani D. Agrawal; Ajoy K. Bose; Patrick Kozak; Hao N. Nham; Ernesto Pacas-Skewes (DAC, 1980)

LSI product quality and fault coverage. - Vishwani D. Agrawal; Sharad C. Seth; Prathima Agrawal (DAC, 1981)

Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. - M. Ray Mercer; Vishwani D. Agrawal; Carlos M. Roman (ITC, 1981)

An Information Theoretic Approach to Digital Fault Testing. - Vishwani D. Agrawal (IEEE Trans. Computers, 1981)

Synchronous path analysis in MOS circuit simulator. - Vishwani D. Agrawal (DAC, 1982)

Testability Measures : What Do They Tell Us ? - Vishwani D. Agrawal; M. Ray Mercer (ITC, 1982)

Test generation for MOS circuits using D-algorithm. - Sunil K. Jain; Vishwani D. Agrawal (DAC, 1983)

Chip layout optimization using critical path weighting. - Alfred E. Dunlop; Vishwani D. Agrawal; David N. Deutsch; M. F. Jukl; Patrick Kozak; Manfred Wiesel (DAC, 1984)

STAFAN: An alternative to fault simulation. - Sunil K. Jain; Vishwani D. Agrawal (DAC, 1984)

A gate level model for CMOS combinational logic circuits with application to fault detection. - Sudhakar M. Reddy; Vishwani D. Agrawal; Sunil K. Jain (DAC, 1984)

Will Testability Analysis Replace Fault Simulation ? - Vishwani D. Agrawal (ITC, 1984)

Characterizing the LSI Yield Equation from Wafer Test Data. - Sharad C. Seth; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

VLSI design process. - Vishwani D. Agrawal; Samuel H. C. Poon (ACM Conference on Computer Science, 1985)

Multiple output minimization. - Prathima Agrawal; Vishwani D. Agrawal; Nripendra N. Biswas (DAC, 1985)

STAFAN Takes a Middle Course. - Vishwani D. Agrawal (ITC, 1985)

Statistical Fault Analysis. - Sunil K. Jain; Vishwani D. Agrawal (IEEE Des. Test, 1985)

Modeling and Test Generation Algorithms for MOS Circuits. - Sunil K. Jain; Vishwani D. Agrawal (IEEE Trans. Computers, 1985)

Deterministic Versus Random Testing. - Vishwani D. Agrawal; M. Ray Mercer (ITC, 1986)

Contest: A Concurrent Test Generator for Sequential Circuits. - Vishwani D. Agrawal; Kwang-Ting Cheng; Prathima Agrawal (DAC, 1988)

A sequential circuit test generation using threshold-value simulation. - Kwang-Ting Cheng; Vishwani D. Agrawal; Ernest S. Kuh (FTCS, 1988)

Automatic test generation using neural networks. - Srimat T. Chakradhar; Michael L. Bushnell; Vishwani D. Agrawal (ICCAD, 1988)

Test generation by fault sampling. - Vishwani D. Agrawal; Hassan Farhat; Sharad Seth (ICCD, 1988)

Designing circuits with partial scan. - Vishwani D. Agrawal; Kwang-Ting Cheng; Daniel D. Johnson 004; Tonysheng Lin (IEEE Des. Test, 1988)

An economical scan design for sequential logic test generation. - Kwang-Ting Cheng; Vishwani D. Agrawal (FTCS, 1989)

State assignment for initializable synthesis (gate level analysis). - Kwang-Ting Cheng; Vishwani D. Agrawal (ICCAD, 1989)

Design of sequential machines for efficient test generation. - Kwang-Ting Cheng; Vishwani D. Agrawal (ICCAD, 1989)

Fault Simulation in a Pipelined Multiprocessor System. - Prathima Agrawal; Vishwani D. Agrawal; Kwang-Ting Cheng; Raffi Tutundjian (ITC, 1989)

A new model for computation of probabilistic testability in combinational circuits. - Sharad C. Seth; Vishwani D. Agrawal (Integr., 1989)

A directed search method for test generation using a concurrent simulator. - Vishwani D. Agrawal; Kwang-Ting Cheng; Prathima Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Test Function Specification in Synthesis. - Vishwani D. Agrawal; Kwang-Ting Cheng (DAC, 1990)

Automatic Test Generation Using Quadratic 0-1 Programming. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1990)

An Entropy Measure for the Complexity of Multi-Output Boolean Functions. - Kwang-Ting Cheng; Vishwani D. Agrawal (DAC, 1990)

An architecture for synthesis of testable finite state machines. - Vishwani D. Agrawal; Kwang-Ting Cheng (EURO-DAC, 1990)

Polynomial time solvable fault detection problems. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell (FTCS, 1990)

Logic Simulation and Parallel Processing. - Vishwani D. Agrawal; Srimat T. Chakradhar (ICCAD, 1990)

An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. - Dharam Vir Das; Sharad C. Seth; Paul T. Wagner; John C. Anderson; Vishwani D. Agrawal (ITC, 1990)

Performance estimation in a massively parallel system. - Vishwani D. Agrawal; Srimat T. Chakradhar (SC, 1990)

Fault Sampling Revisited. - Vishwani D. Agrawal; Hatsuyoshi Kato (IEEE Des. Test Comput., 1990)

Neural Net and Boolean Satisfiability Models of Logic Circuits. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell; Thomas K. Truong (IEEE Des. Test Comput., 1990)

Finite state machine synthesis with embedded test function. - Vishwani D. Agrawal; Kwang-Ting Cheng (J. Electron. Test., 1990)

A Partial Scan Method for Sequential Circuits with Feedback. - Kwang-Ting Cheng; Vishwani D. Agrawal (IEEE Trans. Computers, 1990)

A Simulation-Based Method for Generating Tests for Sequential Circuits. - Kwang-Ting Cheng; Vishwani D. Agrawal; Ernest S. Kuh (IEEE Trans. Computers, 1990)

A Statistical Theory of Digital Circuit Testability. - Sharad C. Seth; Vishwani D. Agrawal; Hassan Farhat (IEEE Trans. Computers, 1990)

Toward massively parallel automatic test generation. - Srimat T. Chakradhar; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A Transitive Closure Based Algorithm for Test Generation. - Srimat T. Chakradhar; Vishwani D. Agrawal (DAC, 1991)

Design and Test-The Two Sides of a Coin. - Vishwani D. Agrawal (ICCD, 1991)

Stafan Algorithms for MOS Circuits. - Joan Villoldo; Prathima Agrawal; Vishwani D. Agrawal (ICCD, 1991)

Estimating the Quality of Manufactured Digital Sequential Circuits. - Dharam Vir Das; Sharad C. Seth; Vishwani D. Agrawal (ITC, 1991)

Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. - Debashis Bhattacharya; Prathima Agrawal; Vishwani D. Agrawal (DAC, 1992)

Delay Fault Models and Test Generation for Random Logic Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1992)

DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits. - Prathima Agrawal; Vishwani D. Agrawal; Sharad C. Seth (EURO-DAC, 1992)

Finite State Machine Testing Based on Growth and Dissappearance Faults. - Mandyam-Komar Srinivas; James Jacob; Vishwani D. Agrawal (FTCS, 1992)

A New Method for Generating Tests for Delay Faults in Non-Scan Circuits. - Prathima Agrawal; Vishwani D. Agrawal; Sharad C. Seth (VLSI Design, 1992)

Functional Test Generation for Sequential Circuits. - James Jacob; Vishwani D. Agrawal (VLSI Design, 1992)

Multiple fault detection in two-level multi-output circuits. - James Jacob; Vishwani D. Agrawal (J. Electron. Test., 1992)

The Comparative and Concurrent Simulation of discrete-event experiments. - Ernst G. Ulrich; Karen Lentz; Jack H. Arabian; Michael Gustin; Vishwani D. Agrawal; Pier Luca Montessoro (J. Electron. Test., 1992)

Initializability Consideration in Sequential Machine Synthesis. - Kwang-Ting Cheng; Vishwani D. Agrawal (IEEE Trans. Computers, 1992)

Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. - Vishwani D. Agrawal; Srimat T. Chakradhar (IEEE Trans. Parallel Distributed Syst., 1992)

Sequential Circuit Test Generation on a Distributed System. - Prathima Agrawal; Vishwani D. Agrawal; Joan Villoldo (DAC, 1993)

Design for Testability for Path Delay faults in Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1993)

Logic systems for path delay test generation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (EURO-DAC, 1993)

Delay fault testability evaluation through timing simulation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1993)

Clock partitioning for testability. - Kent L. Einspahr; Sharad C. Seth; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1993)

Test Pattern Generation for Sequential Circuits on a Network of Workstations. - Prathima Agrawal; Vishwani D. Agrawal; Joan Villoldo (HPDC, 1993)

Generation of Compact Delay Tests by Multiple-Path Activation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (ITC, 1993)

A Synthesis Approach to Design for Testability. - Suman Kanjilal; Srimat T. Chakradhar; Vishwani D. Agrawal (ITC, 1993)

A Path Delay Fault Simulator for Sequential Circuits. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (VLSI Design, 1993)

Partial scan testing with single clock control. - Vishwani D. Agrawal; Tapan J. Chakraborty (VTS, 1993)

Generating Tests for Delay Faults in Nonscan Circuits. - Prathima Agrawal; Vishwani D. Agrawal; Sharad C. Seth (IEEE Des. Test Comput., 1993)

A Tutorial on Built-in Self-Test. I. Principles. - Vishwani D. Agrawal; Charles R. Kime; Kewal K. Saluja (IEEE Des. Test Comput., 1993)

A Tutorial on Built-In Self-Test, Part 2: Applications. - Vishwani D. Agrawal; Charles R. Kime; Kewal K. Saluja (IEEE Des. Test Comput., 1993)

The optimistic update theorem for path delay testing in sequential circuits. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (J. Electron. Test., 1993)

Finite state machine synthesis with fault tolerant test function. - Srimat T. Chakradhar; Suman Kanjilal; Vishwani D. Agrawal (J. Electron. Test., 1993)

A transitive closure algorithm for test generation. - Srimat T. Chakradhar; Vishwani D. Agrawal; Steven G. Rothweiler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Path delay fault simulation of sequential circuits. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Accurate computation of field reject ratio based on fault latency. - D. Das; Sharad C. Seth; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Concurrent and comparative discrete event simulation. - Ernst G. Ulrich; Vishwani D. Agrawal; Jack H. Arabian (Kluwer, 1994)

An Efficient Path Delay Fault Coverage Estimator. - Keerthi Heragu; Michael L. Bushnell; Vishwani D. Agrawal (DAC, 1994)

Delay independent initialization of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1994)

Power Constraint Scheduling of Tests. - Richard M. Chou; Kewal K. Saluja; Vishwani D. Agrawal (VLSI Design, 1994)

A Test Function Architecture for Interconnected Finite State Machines. - Suman Kanjilal; Srimat T. Chakradhar; Vishwani D. Agrawal (VLSI Design, 1994)

An Improved Deductive Fault Simulator. - P. R. Suresh Kumar; James Jacob; Mandyam-Komar Srinivas; Vishwani D. Agrawal (VLSI Design, 1994)

FACTS: fault coverage estimation by test vector sampling. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (VTS, 1994)

A tale of two designs: the cheapest and the most economic. - Vishwani D. Agrawal (J. Electron. Test., 1994)

Energy minimization and design for testability. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell (J. Electron. Test., 1994)

Panel: New Research Problems in the Emerging Test Technology. - Vishwani D. Agrawal; Bernard Courtois; Fumiyasu Hirose; Sandip Kundu; Chung-Len Lee; Yinghua Min; Parimal Pal Chaudhuri (Asian Test Symposium, 1995)

Sequential logic path delay test generation by symbolic analysis. - Soumitra Bose; Vishwani D. Agrawal (Asian Test Symposium, 1995)

Functional test generation for path delay faults. - Mandyam-Komar Srinivas; Vishwani D. Agrawal; Michael L. Bushnell (Asian Test Symposium, 1995)

An adaptive distributed algorithm for sequential circuit test generation. - James Sienicki; Michael L. Bushnell; Prathima Agrawal; Vishwani D. Agrawal (EURO-DAC, 1995)

High-Performance Circuit Testing with Slow-Speed Testers. - Vishwani D. Agrawal; Tapan J. Chakraborty (ITC, 1995)

Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 1995)

Robust testing for stuck-at faults. - Tapan J. Chakraborty; Vishwani D. Agrawal (VLSI Design, 1995)

Statistical methods for delay fault coverage analysis. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 1995)

An efficient automatic test generation system for path delay faults in combinational circuits. - Ananta K. Majhi; James Jacob; Lalit M. Patnaik; Vishwani D. Agrawal (VLSI Design, 1995)

An asynchronous algorithm for sequential circuit test generation on a network of workstations. - James Sienicki; Michael L. Bushnell; Prathima Agrawal; Vishwani D. Agrawal (VLSI Design, 1995)

Functional test generation for non-scan sequential circuits. - Mandyam-Komar Srinivas; James Jacob; Vishwani D. Agrawal (VLSI Design, 1995)

Simulation of at-speed tests for stuck-at faults. - Tapan J. Chakraborty; Vishwani D. Agrawal (VTS, 1995)

Editorial - Special issue on partial scan design. - Vishwani D. Agrawal (J. Electron. Test., 1995)

An exact algorithm for selecting partial scan flip-flops. - Srimat T. Chakradhar; Arun Balakrishnan; Vishwani D. Agrawal (J. Electron. Test., 1995)

Test Generation for Path Delay Faults Using Binary Decision Diagrams. - Debashis Bhattacharya; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Computers, 1995)

Combinational ATPG theorems for identifying untestable faults in sequential circuits. - Vishwani D. Agrawal; Srimat T. Chakradhar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Energy models for delay testing. - Srimat T. Chakradhar; Mahesh A. Iyer; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Fault coverage estimation by test vector sampling. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Test function embedding algorithms with application to interconnected finite state machines. - Suman Kanjilal; Srimat T. Chakradhar; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A partition and resynthesis approach to testable design of large circuits. - Suman Kanjilal; Srimat T. Chakradhar; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Redundancy Identification Using Transitive Closure. - Vishwani D. Agrawal; Michael L. Bushnell; Qing Lin (Asian Test Symposium, 1996)

Improving Circuit Testability by Clock Control. - Kent L. Einspahr; Sharad C. Seth; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1996)

SIGMA: a simulator for segment delay faults. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (ICCAD, 1996)

Synthesis of Self-Testing Finite State Machines from High-Level Specifications. - Vishwani D. Agrawal; Ronald D. Blanton; Maurizio Damiani (ITC, 1996)

An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 1996)

Science, Technology, and the Indian Society. - Vishwani D. Agrawal (VLSI Design, 1996)

Characteristic polynomial method for verification and test of combinational circuits. - Vishwani D. Agrawal; David Lee 001 (VLSI Design, 1996)

Design for high-speed testability of stuck-at faults. - Tapan J. Chakraborty; Vishwani D. Agrawal (VLSI Design, 1996)

Parallel concurrent path-delay fault simulation using single-input change patterns. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 1996)

Improving accuracy in path delay fault coverage estimation. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VLSI Design, 1996)

On test coverage of path delay faults. - Ananta K. Majhi; James Jacob; Lalit M. Patnaik; Vishwani D. Agrawal (VLSI Design, 1996)

Statistical path delay fault coverage estimation for synchronous sequential circuits. - Lakshminarayana Pappu; Michael L. Bushnell; Vishwani D. Agrawal; Mandyam-Komar Srinivas (VLSI Design, 1996)

Segment delay faults: a new fault model. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VTS, 1996)

1995 Asian Test Symposium carves a niche. - Vishwani D. Agrawal (IEEE Des. Test Comput., 1996)

Functional test generation for synchronous sequential circuits. - Mandyam-Komar Srinivas; James Jacob; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Fast identification of untestable delay faults using implications. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (ICCAD, 1997)

Algorithms for Switch Level Delay Fault Simulation. - Soumitra Bose; Vishwani D. Agrawal; Thomas G. Szymanski (ITC, 1997)

Effective Path Selection for Delay Fault Testing of Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal (ITC, 1997)

Low-Power Design by Hazard Filtering. - Vishwani D. Agrawal (VLSI Design, 1997)

Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. - James Jacob; P. Srinivas Sivakumar; Vishwani D. Agrawal (VLSI Design, 1997)

Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. - Mandyam-Komar Srinivas; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 1997)

Power Dissipation During Testing: Should We Worry About it? - Vishwani D. Agrawal; Robert C. Aitken; J. Braden; Joan Figueras; S. Kumar; Hans-Joachim Wunderlich; Yervant Zorian (VTS, 1997)

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (J. Electron. Test., 1997)

On variable clock methods for path delay testing of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Redundancy removal and test generation for circuits with non-Boolean primitives. - Srimat T. Chakradhar; Steven G. Rothweiler; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Improving a nonenumerative method to estimate path delay fault coverage. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Scheduling tests for VLSI systems under power constraints. - Richard M. Chou; Kewal K. Saluja; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1997)

False-Path Removal Using Delay Fault Simulation. - Marwan A. Gharaybeh; Vishwani D. Agrawal; Michael L. Bushnell (Asian Test Symposium, 1998)

Mutually Disjoint Signals and Probability Calculation in Digital Circuits. - Vishwani D. Agrawal; Sharad C. Seth (Great Lakes Symposium on VLSI, 1998)

A non-enumerative path delay fault simulator for sequential circuits. - Carlos G. Parodi; Vishwani D. Agrawal; Michael L. Bushnell; Shianling Wu (ITC, 1998)

Optimizing Logic Design Using Boolean Transforms. - Pramit Chavda; James Jacob; Vishwani D. Agrawal (VLSI Design, 1998)

Mixed-Signal Test. - Ananta K. Majhi; Vishwani D. Agrawal (VLSI Design, 1998)

Tutorial: Delay Fault Models and Coverage. - Ananta K. Majhi; Vishwani D. Agrawal (VLSI Design, 1998)

Path Delay Testing: Variable-Clock Versus Rated-Clock. - Subhashis Majumder; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 1998)

On Delay-Untestable Paths and Stuck-Fault Redundancy. - Subhashis Majumder; Vishwani D. Agrawal; Michael L. Bushnell (VTS, 1998)

Editorial. - Vishwani D. Agrawal (Des. Autom. Embed. Syst., 1998)

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. - Lakshminarayana Pappu; Michael L. Bushnell; Vishwani D. Agrawal; Mandyam-Komar Srinivas (J. Electron. Test., 1998)

Design of mixed-signal systems for testability. - Vishwani D. Agrawal (Integr., 1998)

Numerical computation of characteristic polynomials of Boolean functions and its applications. - Vishwani D. Agrawal; David Lee 001; Henryk Wozniakowski (Numer. Algorithms, 1998)

Deriving Logic Systems for Path Delay Test Generation. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Computers, 1998)

The path-status graph with application to delay fault simulation. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A rated-clock test method for path delay faults. - Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. - Yong Chang Kim; Kewal K. Saluja; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1999)

Panel: Increasing test coverage in a VLSI desgin course. - Vishwani D. Agrawal (ITC, 1999)

Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. - Vishwani D. Agrawal; Michael L. Bushnell; Ganapathy Parthasarathy; Rajesh Ramadoss (VLSI Design, 1999)

A Test Generator for Segment Delay Faults. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VLSI Design, 1999)

A Complete Characterization of Path Delay Faults through Stuck-at Faults. - Subhashis Majumder; Bhargab B. Bhattacharya; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 1999)

Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. - Pradip A. Thaker; Vishwani D. Agrawal; Mona E. Zaghloul (VTS, 1999)

A testability metric for path delay faults and its application. - Huan-Chih Tsai; Kwang-Ting Cheng; Vishwani D. Agrawal (ASP-DAC, 2000)

Testing in the Fourth Dimension. - Vishwani D. Agrawal; Kwang-Ting Cheng (Asian Test Symposium, 2000)

Collaboration between Industry and Academia in Test Research. - Kwang-Ting Cheng; Vishwani D. Agrawal; Jing-Yang Jou; Li-C. Wang; Chi-Feng Wu; Shianling Wu (Asian Test Symposium, 2000)

Compaction-based test generation using state and fault information. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (Asian Test Symposium, 2000)

Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. - José T. de Sousa; Vishwani D. Agrawal (DATE, 2000)

Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. - Pradip A. Thaker; Vishwani D. Agrawal; Mona E. Zaghloul (ITC, 2000)

Choice of Tests for Logic Verification and Equivalence Checking. - Vishwani D. Agrawal (VLSI Design, 2000)

False-Path Removal Using Delay Fault Simulation. - Marwan A. Gharaybeh; Vishwani D. Agrawal; Michael L. Bushnell; Carlos G. Parodi (J. Electron. Test., 2000)

Path delay fault simulation of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Improving path delay testability of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Efficient spectral techniques for sequential ATPG. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (DATE, 2001)

Combinational test generation for various classes of acyclic sequential circuits. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (ITC, 2001)

Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. - Yong Chang Kim; Kewal K. Saluja; Vishwani D. Agrawal (VLSI Design, 2001)

Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (VTS, 2001)

A New Transitive Closure Algorithm with Application to Redundancy Identification. - Vivek Gaur; Vishwani D. Agrawal; Michael L. Bushnell (DELTA, 2002)

A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. - A. V. S. S. Prasad; Vishwani D. Agrawal; Madhusudan V. Atre (ITC, 2002)

Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. - Aditya D. Sathe; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 2002)

Electronic Testing for SOC Designers (Tutorial Abstract). - Vishwani D. Agrawal; Michael L. Bushnell (ASP-DAC/VLSI Design, 2002)

Multiple Faults: Modeling, Simulation and Test. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (ASP-DAC/VLSI Design, 2002)

State and Fault Information for Compaction-Based Test Generation. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (J. Electron. Test., 2002)

Fault Collapsing via Functional Dominance. - Vishwani D. Agrawal; A. V. S. S. Prasad; Madhusudan V. Atre (ITC, 2003)

Exclusive Test and its Applications to Fault Diagnosis. - Vishwani D. Agrawal; Dong Hyun Baik; Yong Chang Kim; Kewal K. Saluja (VLSI Design, 2003)

A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. - Vishal J. Mehta; Kunal K. Dave; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2003)

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2003)

New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. - Lan Rao; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 2003)

A test evaluation technique for VLSI circuits using register-transfer level fault modeling. - Pradip A. Thaker; Vishwani D. Agrawal; Mona E. Zaghloul (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. - Junwu Zhang; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 2004)

A Tuturial on the Emerging Nanotechnology Devices. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2004)

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2004)

1985 to 1987: My years with D&T. - Vishwani D. Agrawal (IEEE Des. Test Comput., 2004)

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. - Subhashis Majumder; Bhargab B. Bhattacharya; Vishwani D. Agrawal; Michael L. Bushnell (J. Comput. Sci. Technol., 2004)

Concurrent Test Generation. - Vishwani D. Agrawal; Alok S. Doshi (Asian Test Symposium, 2005)

Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. - Raja K. K. R. Sandireddy; Vishwani D. Agrawal (DATE, 2005)

Dual-transition glitch filtering in probabilistic waveform power estimation. - Fei Hu; Vishwani D. Agrawal (ACM Great Lakes Symposium on VLSI, 2005)

Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. - Fei Hu; Vishwani D. Agrawal (ICCD, 2005)

A random access scans architecture to reduce hardware overhead. - Anand S. Mudlapur; Vishwani D. Agrawal; Adit D. Singh (ITC, 2005)

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. - Yuanlin Lu; Vishwani D. Agrawal (PATMOS, 2005)

Design of Variable Input Delay Gates for Low Dynamic Power Circuits. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (PATMOS, 2005)

Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. - Kunal K. Dave; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2005)

Combinational automatic test pattern generation for acyclic sequential circuits. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Spectral RTL Test Generation for Gate-Level Stuck-at Faults. - Nitin Yogi; Vishwani D. Agrawal (ATS, 2006)

Input-specific dynamic power optimization for VLSI circuits. - Fei Hu; Vishwani D. Agrawal (ISLPED, 2006)

Fault Coverage Estimation for Non-Random Functional Input Sequences. - Soumitra Bose; Vishwani D. Agrawal (ITC, 2006)

Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. - Vishwani D. Agrawal; Soumitra Bose; Vijay Gangaram (VTS, 2006)

CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. - Yuanlin Lu; Vishwani D. Agrawal (J. Low Power Electron., 2006)

Transistor Sizing of Logic Gates to Maximize Input Delay Variability. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (J. Low Power Electron., 2006)

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. - Soumitra Bose; Vishwani D. Agrawal (ITC, 2007)

Delay fault simulation with bounded gate delay mode. - Soumitra Bose; Hillary Grimes; Vishwani D. Agrawal (ITC, 2007)

SPARTAN: a spectral and information theoretic approach to partial-scan. - Omar I. Khan; Michael L. Bushnell; Suresh Kumar Devanathan; Vishwani D. Agrawal (ITC, 2007)

A Reduced Complexity Algorithm for Minimizing N-Detect Tests. - Kalyana R. Kantipudi; Vishwani D. Agrawal (VLSI Design, 2007)

Statistical Leakage and Timing Optimization for Submicron Process Variation. - Yuanlin Lu; Vishwani D. Agrawal (VLSI Design, 2007)

Spectral RTL Test Generation for Microprocessors. - Nitin Yogi; Vishwani D. Agrawal (VLSI Design, 2007)

Delay Test Quality Evaluation Using Bounded Gate Delays. - Soumitra Bose; Vishwani D. Agrawal (VTS, 2007)

Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. - Lan Rao; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns. - Nitin Yogi; Vishwani D. Agrawal (ATS, 2008)

A tutorial on test power. - Vishwani D. Agrawal (ISLPED, 2008)

Built-in Self-Calibration of On-chip DAC and ADC. - Wei Jiang; Vishwani D. Agrawal (ITC, 2008)

Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. - Yuanlin Lu; Vishwani D. Agrawal (VLSI Design, 2008)

Single Event Upset: An Embedded Tutorial. - Fan Wang; Vishwani D. Agrawal (VLSI Design, 2008)

Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. - Rajamani Sethuram; Michael L. Bushnell; Vishwani D. Agrawal (VTS, 2008)

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (Asian Test Symposium, 2009)

A Two Phase Approach for Minimal Diagnostic Test Set Generation. - Mohammed Ashfaq Shukoor; Vishwani D. Agrawal (ETS, 2009)

On Minimization of Peak Power for Scan Circuit during Test. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Vishwani D. Agrawal (ETS, 2009)

Polynomial coefficient based DC testing of non-linear analog circuits. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (ACM Great Lakes Symposium on VLSI, 2009)

Designing Variation-tolerance in Mixed-signal Components of a System-on-chip. - Wei Jiang; Vishwani D. Agrawal (ISCAS, 2009)

Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. - Jins D. Alexander; Vishwani D. Agrawal (ISVLSI, 2009)

Soft Error Rates with Inertial and Logical Masking. - Fan Wang; Vishwani D. Agrawal (VLSI Design, 2009)

Output Hazard-Free Transition Delay Fault Test Generation. - Sreekumar Menon; Adit D. Singh; Vishwani D. Agrawal (VTS, 2009)

Variable Input Delay CMOS Logic for Low Power Design. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A diagnostic test generation system and a coverage metric. - Yu Zhang; Vishwani D. Agrawal (ETS, 2010)

Soft error rate determination for nanoscale sequential logic. - Fan Wang; Vishwani D. Agrawal (ISQED, 2010)

A diagnostic test generation system. - Yu Zhang; Vishwani D. Agrawal (ITC, 2010)

An algorithm for diagnostic fault simulation. - Yu Zhang; Vishwani D. Agrawal (LATW, 2010)

Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (VLSI Design, 2010)

Application of signal and noise theory to digital VLSI testing. - Nitin Yogi; Vishwani D. Agrawal (VTS, 2010)

Test and Diagnosis of Analog Circuits Using Moment Generating Functions. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (Asian Test Symposium, 2011)

Reduced complexity test generation algorithms for transition fault diagnosis. - Yu Zhang; Vishwani D. Agrawal (ICCD, 2011)

Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. - Kyungseok Kim; Vishwani D. Agrawal (ISQED, 2011)

Testing for faults, looking for defects. - Vishwani D. Agrawal (LATW, 2011)

Testing linear and non-linear analog circuits using moment generating functions. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (LATW, 2011)

True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. - Kyungseok Kim; Vishwani D. Agrawal (VLSI Design, 2011)

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. - Srinivasulu Alampally; R. T. Venkatesh; Priyadharshini Shanmugasundaram; Rubin A. Parekhji; Vishwani D. Agrawal (VTS, 2011)

Dynamic scan clock control for test time reduction maintaining peak power limit. - Priyadharshini Shanmugasundaram; Vishwani D. Agrawal (VTS, 2011)

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (VTS, 2011)

Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. - Kyungseok Kim; Vishwani D. Agrawal (J. Low Power Electron., 2011)

Tailoring Tests for Functional Binning of Integrated Circuits. - Suraj Sindia; Vishwani D. Agrawal (Asian Test Symposium, 2012)

Impact of process variations on computers used for image processing. - Suraj Sindia; Fa Foster Dai; Vishwani D. Agrawal; Virendra Singh (ISCAS, 2012)

Retiming scan circuit to eliminate timing penalty. - Ozgur Sinanoglu; Vishwani D. Agrawal (LATW, 2012)

Optimal power-constrained SoC test schedules with customizable clock rates. - Vijay Sheshadri; Vishwani D. Agrawal; Prathima Agrawal (SoCC, 2012)

Power Problems in VLSI Circuit Testing. - Farhana Rashid; Vishwani D. Agrawal (VDAT, 2012)

Keynote Talk: A History of the VLSI Design Conference. - Vishwani D. Agrawal (VLSI Design, 2012)

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. - Priyadharshini Shanmugasundaram; Vishwani D. Agrawal (VLSI Design, 2012)

Towards spatial fault resilience in array processors. - Suraj Sindia; Vishwani D. Agrawal (VTS, 2012)

Net diagnosis using stuck-at and transition fault models. - Lixing Zhao; Vishwani D. Agrawal (VTS, 2012)

Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®. - Kanad Chakraborty; Vishwani D. Agrawal (J. Electron. Test., 2012)

Diagnostic Test Set Minimization and Full-Response Fault Dictionary. - Mohammed Ashfaq Shukoor; Vishwani D. Agrawal (J. Electron. Test., 2012)

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (J. Electron. Test., 2012)

Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (J. Electron. Test., 2012)

Yield analysis of a novel wafer manipulation method in 3D stacking. - Bei Zhang; Baohu Li; Vishwani D. Agrawal (3DIC, 2013)

High sensitivity test signatures for unconventional analog circuit test paradigms. - Suraj Sindia; Vishwani D. Agrawal (ITC, 2013)

ATE test time reduction using asynchronous clock period. - Praveen Venkataramani; Vishwani D. Agrawal (ITC, 2013)

Defect Diagnosis of Digital Circuits Using Surrogate Faults. - Chidambaram Alagappan; Vishwani D. Agrawal (VDAT, 2013)

Power-aware SoC test optimization through dynamic voltage and frequency scaling. - Vijay Sheshadri; Vishwani D. Agrawal; Prathima Agrawal (VLSI-SoC, 2013)

Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. - Vijay Sheshadri; Vishwani D. Agrawal; Prathima Agrawal (VLSI Design, 2013)

Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. - Praveen Venkataramani; Vishwani D. Agrawal (VLSI Design, 2013)

Finding best voltage and frequency to shorten power-constrained test time. - Praveen Venkataramani; Suraj Sindia; Vishwani D. Agrawal (VTS, 2013)

Eliminating the Timing Penalty of Scan. - Ozgur Sinanoglu; Vishwani D. Agrawal (J. Electron. Test., 2013)

Neural Network Guided Spatial Fault Resilience in Array Processors. - Suraj Sindia; Vishwani D. Agrawal (J. Electron. Test., 2013)

Energy-Efficient Dual-Voltage Design Using Topological Constraints. - Mridula Allani; Vishwani D. Agrawal (J. Low Power Electron., 2013)

An optimized diagnostic procedure for pre-bond TSV defects. - Bei Zhang; Vishwani D. Agrawal (ICCD, 2014)

Specification test minimization for given defect level. - Suraj Sindia; Vishwani D. Agrawal (LATW, 2014)

Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock. - Sindhu Gunasekar; Vishwani D. Agrawal (NATW, 2014)

A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation. - Muralidharan Venkatasubramanian; Vishwani D. Agrawal (NATW, 2014)

A Test Time Theorem and its Applications. - Praveen Venkataramani; Suraj Sindia; Vishwani D. Agrawal (J. Electron. Test., 2014)

A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs. - Bei Zhang; Vishwani D. Agrawal (J. Electron. Test., 2014)

Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools. - Yu Zhang; Bei Zhang; Vishwani D. Agrawal (J. Electron. Test., 2014)

A Four-Transistor Level Converter for Dual-Voltage Low-Power Design. - Karthik Naishathrala Jayaraman; Vishwani D. Agrawal (J. Low Power Electron., 2014)

Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key. - Hejia Liu; Vishwani D. Agrawal (ATS, 2015)

Quest for a quantum search algorithm for testing stuck-at faults in digital circuits. - Muralidharan Venkatasubramanian; Vishwani D. Agrawal; James J. Janaher (DFTS, 2015)

Message from the LATS2015 Chairs. - Víctor H. Champac; Yervant Zorian; Letícia Maria Bolzani Pöhls; Vishwani D. Agrawal (LATS, 2015)

Adopting multi-valued logic for reduced pin-count testing. - Baohu Li; Bei Zhang; Vishwani D. Agrawal (LATS, 2015)

Characterizing Processors for Energy and Performance Management. - Harshit Goyal; Vishwani D. Agrawal (MTV, 2015)

Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing. - Baohu Li; Vishwani D. Agrawal (NATW, 2015)

SoC TAM Design to Minimize Test Application Time. - Huiting Zhang; Vishwani D. Agrawal (NATW, 2015)

Few Good Frequencies for Power-Constrained Test. - Sindhu Gunasekar; Vishwani D. Agrawal (VLSID, 2015)

Diagnostic Tests for Pre-bond TSV Defects. - Bei Zhang; Vishwani D. Agrawal (VLSID, 2015)

A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing. - Sindhu Gunasekar; Vishwani D. Agrawal (J. Electron. Test., 2015)

Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. - Suraj Sindia; Vishwani D. Agrawal (J. Electron. Test., 2015)

Failures Guide Probabilistic Search for a Hard-to-Find Test. - Muralidharan Venkatasubramanian; Vishwani D. Agrawal (NATW, 2016)

Database Search and ATPG - Interdisciplinary Domains and Algorithms. - Muralidharan Venkatasubramanian; Vishwani D. Agrawal (VLSID, 2016)

Applications of Mixed-Signal Technology in Digital Testing. - Baohu Li; Vishwani D. Agrawal (J. Electron. Test., 2016)

Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling. - Vijay Sheshadri; Vishwani D. Agrawal; Prathima Agrawal (J. Electron. Test., 2017)

Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. - Bei Zhang; Vishwani D. Agrawal (J. Electron. Test., 2017)

Modeling and test generation for combinational hardware Trojans. - Ziqi Zhou; Ujjwal Guin; Vishwani D. Agrawal (VTS, 2018)

Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. - Spencer K. Millican; Yang Sun; Soham Roy; Vishwani D. Agrawal (ATS, 2019)

Improved Random Pattern Delay Fault Coverage Using Inversion Test Points. - Soham Roy; Brandon Stiene; Spencer K. Millican; Vishwani D. Agrawal (NATW, 2019)

Technology Characterization Model and Scaling for Energy Management. - Harshil Goyal; Vishwani D. Agrawal (VDAT, 2019)

Two-Pattern ∆IDDQ Test for Recycled IC Detection. - Prattay Chowdhury; Ujjwal Guin; Adit D. Singh; Vishwani D. Agrawal (VLSID, 2019)

Energy Efficient Power Distribution on Many-Core SoC. - Mustafa M. Shihab; Vishwani D. Agrawal (VLSID, 2019)

Special Session: Delay Fault Testing - Present and Future. - Jubayer Mahmod; Spencer K. Millican; Ujjwal Guin; Vishwani D. Agrawal (VTS, 2019)

Machine Intelligence for Efficient Test Pattern Generation. - Soham Roy; Spencer K. Millican; Vishwani D. Agrawal (ITC, 2020)

Message from the Steering Committee Chair. - Vishwani D. Agrawal (VLSID, 2020)

Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. - Yang Sun; Spencer K. Millican; Vishwani D. Agrawal (VTS, 2020)

Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures. - Soham Roy; Brandon Stiene; Spencer K. Millican; Vishwani D. Agrawal (J. Electron. Test., 2020)

Unsupervised Learning in Test Generation for Digital Integrated Circuits. - Soham Roy; Spencer K. Millican; Vishwani D. Agrawal (ETS, 2021)

Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. - Soham Roy; Spencer K. Millican; Vishwani D. Agrawal (VLSID, 2021)

Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits. - Soham Roy; Spencer K. Millican; Vishwani D. Agrawal (VTS, 2021)

Defect Characterization and Testing of Skyrmion-Based Logic Circuits. - Ziqi Zhou; Ujjwal Guin; Peng Li; Vishwani D. Agrawal (VTS, 2021)

Estimating Operational Age of an Integrated Circuit. - Prattay Chowdhury; Ujjwal Guin; Adit D. Singh; Vishwani D. Agrawal (J. Electron. Test., 2021)

Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits. - Ziqi Zhou; Ujjwal Guin; Peng Li; Vishwani D. Agrawal (VTS, 2022)

Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults. - Soham Roy; Vishwani D. Agrawal (ITC, 2024)

An Amalgamated Testability Measure Derived from Machine Intelligence. - Soham Roy; Vishwani D. Agrawal (VLSID, 2024)

A Survey and Recent Advances: Machine Intelligence in Electronic Testing. - Soham Roy; Spencer K. Millican; Vishwani D. Agrawal (J. Electron. Test., 2024)