A 225 MHz resonant clocked ASIC chip. - Conrad H. Ziesler; Joohee Kim; Visvesh S. Sathe 001; Marios C. Papaefthymiou (ISLPED, 2003)

A synchronous interface for SoCs with multiple clock domains. - Visvesh S. Sathe 001; Conrad H. Ziesler; Marios C. Papaefthymiou; Suhwan Kim 001; Stephen V. Kosonocky (SoCC, 2004)

Fast, efficient, recovering, and irreversible. - Visvesh S. Sathe 001; Juang-Ying Chueh; Joohee Kim; Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (Conf. Computing Frontiers, 2005)

A GHz-class charge recovery logic. - Visvesh S. Sathe 001; Marios C. Papaefthymiou; Conrad H. Ziesler (ISLPED, 2005)

Boost Logic: A High Speed Energy Recovery Circuit Family. - Visvesh S. Sathe 001; Marios C. Papaefthymiou; Conrad H. Ziesler (ISVLSI, 2005)

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. - Juang-Ying Chueh; Visvesh S. Sathe 001; Marios C. Papaefthymiou (CICC, 2006)

A 1.1ghz charge-recovery logic. - Visvesh S. Sathe 001; Juang-Ying Chueh; Marios Papaefthymio (ISSCC, 2006)

A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. - Visvesh S. Sathe 001; Jerry C. Kao; Marios C. Papaefthymiou (CICC, 2007)

Energy-Efficient GHz-Class Charge-Recovery Logic. - Visvesh S. Sathe 001; Juang-Ying Chueh; Marios C. Papaefthymiou (IEEE J. Solid State Circuits, 2007)

Resonant-Clock Latch-Based Design. - Visvesh S. Sathe 001; Jerry C. Kao; Marios C. Papaefthymiou (IEEE J. Solid State Circuits, 2008)

A resonant-clock 200MHz ARM926EJ-STM microcontroller. - Alexander T. Ishii; Jerry C. Kao; Visvesh S. Sathe 001; Marios C. Papaefthymiou (ESSCIRC, 2009)

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. - Jerry C. Kao; Wei-Hsiang Ma; Visvesh S. Sathe 001; Marios C. Papaefthymiou (ESSCIRC, 2009)

A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency. - Hanh-Phuc Le; Michael D. Seeman; Seth Sanders; Visvesh S. Sathe 001; Samuel Naffziger; Elad Alon (ISSCC, 2010)

187 MHz Subthreshold-Supply Charge-Recovery FIR. - Wei-Hsiang Ma; Jerry C. Kao; Visvesh S. Sathe 001; Marios C. Papaefthymiou (IEEE J. Solid State Circuits, 2010)

Advances in 3D design and optimization. - Steven J. E. Wilton; Visvesh S. Sathe 001 (CICC, 2012)

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. - Jerry C. Kao; Wei-Hsiang Ma; Visvesh S. Sathe 001; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Energy efficient SoC design. - Visvesh S. Sathe 001; Arif Rahman (CICC, 2013)

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. - Visvesh S. Sathe 001; Srikanth Arekapudi; Alexander T. Ishii; Charles Ouyang; Marios C. Papaefthymiou; Samuel Naffziger (IEEE J. Solid State Circuits, 2013)

A deterministic-dither-based, all-digital system for on-chippower supply noise measurement. - Kannan A. Sankaragomathi; William Anthony Smith; Brian P. Otis; Visvesh S. Sathe 001 (ISLPED, 2014)

Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability. - Visvesh S. Sathe 001 (ISLPED, 2014)

Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS. - Xiaoyang Mi; Debashis Mandal; Visvesh S. Sathe 001; Bertan Bakkaloglu; Jae-sun Seo (ISLPED, 2015)

Analysis and optimization of CMOS switched-capacitor converters. - Visvesh S. Sathe 001; Jae-sun Seo (ISLPED, 2015)

All-digital hybrid-control buck converter for Integrated Voltage Regulator applications. - Ta-Tung Yen; Bin Yu; Visvesh S. Sathe 001 (DATE, 2016)

UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction. - Samantak Gangopadhyay; Saad Bin Nasir; A. Subramanian; Visvesh Sathe 001; Arijit Raychowdhury (ESSCIRC, 2016)

Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip. - Ali Najafi; Jacques Christophe Rudell; Visvesh Sathe 001 (ISLPED, 2016)

19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. - Fahim U. Rahman; Visvesh S. Sathe 001 (ISSCC, 2016)

Tutorial 4A: Supply voltage noise and mitigation for real world SoCs. - Visvesh Sathe 001; Andrew Marshall (SoCC, 2016)

Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference. - Patrick Chiang 001; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2016)

Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements. - William Anthony Smith; Brian Mogen; Eberhard E. Fetz; Visvesh S. Sathe 001; Brian P. Otis (IEEE Trans. Biomed. Circuits Syst., 2016)

Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. - Vincent T. Lee; Armin Alaghi; John P. Hayes; Visvesh Sathe 001; Luis Ceze (DATE, 2017)

Exploring computation-communication tradeoffs in camera systems. - Amrita Mazumdar; Thierry Moreau; Sung Kim; Meghan Cowan; Armin Alaghi; Luis Ceze; Mark Oskin; Visvesh Sathe 001 (IISWC, 2017)

MATIC: Learning around errors for efficient low-voltage neural network accelerators. - Sung Kim; Patrick Howe; Thierry Moreau; Armin Alaghi; Luis Ceze; Visvesh Sathe 001 (DATE, 2018)

A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. - Xun Sun; Sung Kim; Fahim ur Rahman; Venkata Rajesh Pamula 001; Xi Li; Naveen John; Visvesh S. Sathe 001 (ISSCC, 2018)

An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. - Rajesh Pamula 001; Xun Sun; Sung Kim; Fahim ur Rahman; Baosen Zhang; Visvesh S. Sathe 001 (VLSI Circuits, 2018)

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. - Fahim ur Rahman; Sung Kim; Naveen John; Roshan Kumar; Xi Li; Rajesh Pamula 001; Keith A. Bowman; Visvesh S. Sathe 001 (VLSI Circuits, 2018)

Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems. - Fahim U. Rahman; Visvesh Sathe 001 (IEEE J. Solid State Circuits, 2018)

Architecture Considerations for Stochastic Computing Accelerators. - Vincent T. Lee; Armin Alaghi; Rajesh Pamula 001; Visvesh S. Sathe 001; Luis Ceze; Mark Oskin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors. - Sung Kim; Patrick Howe; Thierry Moreau; Armin Alaghi; Luis Ceze; Visvesh S. Sathe 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. - Xiyuan Tang; Yi Shen 007; Linxiao Shen; Wenda Zhao; Zhangming Zhu; Visvesh Sathe 001; Nan Sun 001 (CICC, 2019)

A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS. - John P. Uehlin; William Anthony Smith; Venkata Rajesh Pamula 001; Steve I. Perlmutter; Visvesh Sathe 001; Jacques Christophe Rudell (ESSCIRC, 2019)

Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. - Fahim ur Rahman; Rajesh Pamula 001; Akshat Boora; Xun Sun; Visvesh Sathe 001 (ISSCC, 2019)

A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. - Xun Sun; Akshat Boora; Wenbing Zhang; Venkata Rajesh Pamula 001; Visvesh Sathe 001 (ISSCC, 2019)

Bandwidth Extension on Raw Audio via Generative Adversarial Networks. - Sung Kim; Visvesh Sathe 001 (CoRR, 2019)

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. - Fahim ur Rahman; Sung Kim; Naveen John; Roshan Kumar; Xi Li; Rajesh Pamula 001; Keith A. Bowman; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2019)

A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation. - Fahim ur Rahman; Greg Taylor; Visvesh Sathe 001 (IEEE J. Solid State Circuits, 2019)

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. - Xun Sun; Fahim ur Rahman; Venkata Rajesh Pamula 001; Sung Kim; Xi Li; Naveen John; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2019)

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. - Fahim ur Rahman; Rajesh Pamula 001; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2020)

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. - Yi Shen 007; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Xin Xin 005; Shubin Liu; Zhangming Zhu; Visvesh Sathe 001; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS. - John P. Uehlin; William Anthony Smith; Venkata Rajesh Pamula 001; Eric P. Pepin; Steve I. Perlmutter; Visvesh Sathe 001; Jacques Christophe Rudell (IEEE J. Solid State Circuits, 2020)

A 0.0023 mm2/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression. - John P. Uehlin; William Anthony Smith; Venkata Rajesh Pamula 001; Steve I. Perlmutter; Jacques Christophe Rudell; Visvesh S. Sathe 001 (IEEE Trans. Biomed. Circuits Syst., 2020)

A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation. - Arindam Mandal; Diego Peña; Rajesh Pamula 001; Karam Khateeb; Logan Murphy; Azadeh Yazdan-Shahmorad; Steve I. Perlmutter; Forrest Pape; Jacques Christophe Rudell; Visvesh S. Sathe 001 (CICC, 2021)

A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. - Chi-Hsiang Huang 001; Xun Sun; Yidong Chen 005; Rajesh Pamula 001; Arindam Mandal; Visvesh Sathe 001 (ISSCC, 2021)

A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver. - Deniz Dosluoglu; Kun-Da Chu; Diego Peña-Colaiocco; Ivan Zhao; Visvesh Sathe 001; Jacques C. Rudell (ESSCIRC, 2022)

CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. - Sumanth Gudaparthi; Sarabjeet Singh; Surya Narayanan; Rajeev Balasubramonian; Visvesh Sathe 001 (HPCA, 2022)

Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. - Chi-Hsiang Huang 001; Arindam Mandal; Diego Peña-Colaiocco; Edevaldo Pereira Da Silva; Visvesh S. Sathe 001 (ISSCC, 2022)

An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. - Diego Peña-Colaiocco; Chi-Hsiang Huang 001; Kun-Da Chu; Jacques Christophe Rudell; Visvesh S. Sathe 001 (ISSCC, 2022)

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS. - James D. Rosenthal; Arindam Mandal; Visvesh Sathe 001; Matthew S. Reynolds (RFID, 2022)

Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. - Chi-Hsiang Huang 001; Yidong Chen 005; Xun Sun; Arindam Mandal; Venkata Rajesh Pamula 001; Nasser A. Kurd; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2022)

Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. - Chi-Hsiang Huang 001; Arindam Mandal; Diego Peña-Colaiocco; Edevaldo Pereira Da Silva; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2023)

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). - Mike Shuo-Wei Chen; Visvesh S. Sathe 001; Massimo Alioto; Jae-Sun Seo; Hidehiro Shiga (IEEE J. Solid State Circuits, 2024)

A 95.9-dB SNDR 10-kHz BW 3rd-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer. - Ken Li; Wei-En Lee; Xitie Zhang; Tian Xie 006; Tzu-Han Wang; Visvesh Sathe 001; Shaolan Li (CICC, 2025)

A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery. - Arindam Mandal; Chi-Hsiang Huang 001; Julian Arenas; Wei-En Lee; Philip Anschutz; Amanda L. Jacob; Keshav Ramachandra; Samuel J. Sober; Muhannad S. Bakir; Shaolan Li; Visvesh S. Sathe 001 (CICC, 2025)

A 0.14µJ Per-Acquisition Frequency Domain GPS Correlator Using Adaptive Compressive Sampling. - Jung-Jin Park; Julian Arenas; Kevin Patino-Sosa; Visvesh S. Sathe 001 (CICC, 2025)

A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression. - Tzu-Han Wang; Chenyang Li; Dong Suk Kang; Ken Li; Xitie Zhang; Wei-En Lee; Visvesh Sathe 001; Shaolan Li (CICC, 2025)

A Dynamically Reconfigurable Digital-Integrated Voltage-Regulator Fabric for Energy-Efficient DVFS in Multi-Domain soCs. - Julian Arenas; Chi-Hsiang Huang 003; Kevin Patino-Sosa; Jung-Jin Park; Hikmet Seha Ozturk; Visvesh Sathe 001 (ISSCC, 2025)

8.7 A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS. - Hikmet Seha Ozturk; Julian Arenas; Carlos Tokunaga; Nasser A. Kurd; Visvesh Sathe 001 (ISSCC, 2025)