Design and analysis of ultra-thin-body SOI based subthreshold SRAM. - Vita Pi-Ho Hu; Yu-Sheng Wu; Ming-Long Fan; Pin Su; Ching-Te Chuang (ISLPED, 2009)

Analysis of power-performance for ultra-thin-body GeOI logic circuits. - Vita Pi-Ho Hu; Ming-Long Fan; Pin Su; Ching-Te Chuang (ISLPED, 2011)

Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. - Vita Pi-Ho Hu; Ming-Long Fan; Pin Su; Ching-Te Chuang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. - Chia-Hao Pao; Ming-Long Fan; Ming-Fu Tsai; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (APCCAS, 2012)

A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Ming-Fu Tsai; Chia-Hao Pao; Pin Su; Ching-Te Chuang (ESSDERC, 2012)

Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. - Vita Pi-Ho Hu; Ming-Long Fan; Pin Su; Ching-Te Chuang (ESSDERC, 2012)

Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. - Chia-Hao Pao; Ming-Long Fan; Ming-Fu Tsai; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ICICDT, 2012)

Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. - Ming-Long Fan; Vita Pi-Ho Hu; Yin-Nien Chen; Pin Su; Ching-Te Chuang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. - Chien-Yu Hsieh; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. - Shao-Yu Yang; Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ICICDT, 2013)

Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. - Vita Pi-Ho Hu; Ming-Long Fan; Pin Su; Ching-Te Chuang (ISQED, 2013)

Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. - Ming-Long Fan; Vita Pi-Ho Hu; Yin-Nien Chen; Pin Su; Ching-Te Chuang (ISCAS, 2014)

Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. - Vita Pi-Ho Hu; Ming-Long Fan; Pin Su; Ching-Te Chuang (ISCAS, 2014)

Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ISLPED, 2014)

Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. - Ming-Long Fan; Shao-Yu Yang; Vita Pi-Ho Hu; Yin-Nien Chen; Pin Su; Ching-Te Chuang (Microelectron. Reliab., 2014)

Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. - Tse-Ching Wu; Chien-Ju Chen; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ICICDT, 2015)

Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. - Chien-Ju Chen; Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ISCAS, 2015)

Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. - Vita Pi-Ho Hu; Ming-Long Fan; Pin Su; Ching-Te Chuang (ISCAS, 2015)

Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. - Tse-Ching Wu; Chien-Ju Chen; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (SoCC, 2015)

Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. - Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ISCAS, 2016)

Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation. - Zhe-An Zheng; Vita Pi-Ho Hu (ISCAS, 2019)

Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET. - Hung-Han Lin; Vita Pi-Ho Hu (ISQED, 2019)

Improved Energy Efficiency for Ferroelectric FET Non-Volatile Memory using Split-Gate Design. - Yen-Wei Lee; Vita Pi-Ho Hu (ISCAS, 2020)

Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node. - Vita Pi-Ho Hu; Cheng-Wei Su; Chun-Chi Yu; Chang-Ju Liu; Cheng-Yang Weng (ISCAS, 2021)

Energy-Efficient SRAM with Emerging Technologies. - Vita Pi-Ho Hu (ICICDT, 2023)

Improved RF Performance with Buried Power Rail and Contact over Active Gate in Nanosheet FETs. - Hao-Chi Chiu; Vita Pi-Ho Hu (ISCAS, 2024)

Uncertainty-Aware LiDAR-Camera Autonomy via Conformal Prediction and Principled Abstention. - Divake Kumar; Sina Tayebati; Nastaran Darabi; Vita Pi-Ho Hu; Amit Ranjan Trivedi (COINS, 2025)

Design Technology Co-Optimization for CFET SRAM Cells Considering Double-Sided Signal/Power Routing. - Yu-Cheng Lu; Meng-Lin Wu; Vita Pi-Ho Hu (ISCAS, 2025)