Testing the double low-IF receiver architecture. - Vito Boccuzzi; Jack P. F. Glas (PIMRC, 1998)

7V tristate-capable output buffer implemented in standard 2.5 V CMOS process. - Vladimir I. Prodanov; Vito Boccuzzi (CICC, 2001)

A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications. - Carlo Samori; Salvatore Levantino; Vito Boccuzzi (CICC, 2001)

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. - Salvatore Levantino; Carlo Samori; Andrea Bonfanti; Sander L. J. Gierkink; Andrea L. Lacaita; Vito Boccuzzi (IEEE J. Solid State Circuits, 2002)

A power efficient channel selection filter/coarse AGC with no range switching transients. - Yorgos Palaskas; Yannis P. Tsividis; Vito Boccuzzi (CICC, 2003)

Differentially "bathtub"-tuned CMOS VCO using inductively coupled varactors. - Sander L. J. Gierkink; Robert C. Frye; Vito Boccuzzi (ESSCIRC, 2003)

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling. - Sander L. J. Gierkink; Salvatore Levantino; Robert C. Frye; Carlo Samori; Vito Boccuzzi (IEEE J. Solid State Circuits, 2003)

A CMOS GSM IF-sampling circuit with reduced in-channel aliasing. - Salvatore Levantino; Carlo Samori; Mihai Banu; Jack P. F. Glas; Vito Boccuzzi (IEEE J. Solid State Circuits, 2003)

A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver. - Sander L. J. Gierkink; Dandan Li; Robert C. Frye; Vito Boccuzzi (CICC, 2004)

Low-power pipeline ADC for wireless LANs. - Jesús Arias Álvarez; Vito Boccuzzi; Luis Quintanilla; Lourdes Enríquez; David Bisbal; Mihai Banu; Juan Barbolla (IEEE J. Solid State Circuits, 2004)

A "divide and conquer" technique for implementing wide dynamic range continuous-time filters. - Yorgos Palaskas; Yannis P. Tsividis; Vladimir I. Prodanov; Vito Boccuzzi (IEEE J. Solid State Circuits, 2004)

A robust 43-GHz VCO in CMOS for OC-768 SONET applications. - Arnoud P. van der Wel; Sander L. J. Gierkink; Robert C. Frye; Vito Boccuzzi; Bram Nauta (IEEE J. Solid State Circuits, 2004)

Stable high-order delta-sigma digital-to-analog converters. - Peter Kiss; Jesús Arias Álvarez; Dandan Li; Vito Boccuzzi (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver. - Sander L. J. Gierkink; Dandan Li; Robert C. Frye; Vito Boccuzzi (IEEE J. Solid State Circuits, 2005)

Nonlinearity correction for multibit ΔΣ DACs. - Jesús Arias Álvarez; Peter Kiss; Vito Boccuzzi; Luis Quintanilla; Lourdes Enríquez; José Vicente; David Bisbal; Jacinto San Pablo; Juan Barbolla (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers. - Jesús Arias Álvarez; Peter Kiss; Vladimir I. Prodanov; Vito Boccuzzi; Mihai Banu; David Bisbal; Jacinto San Pablo; Luis Quintanilla; Juan Barbolla (IEEE J. Solid State Circuits, 2006)

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links. - Kadaba Lakshmikumar; Alexander Kurylak; Manohar Nagaraju; Richard Booth 004; Romesh Kumar Nandwana; Joe Pampanin; Vito Boccuzzi (IEEE J. Solid State Circuits, 2019)

High-Performance CMOS TIA for Data Center Optical Interconnects. - Kadaba R. Lakshmikumar; Alexander Kurylak; Romesh Kumar Nandwana; Bibhu Das; Joe Pampanin; Vito Boccuzzi; Pavan Kumar Hanumolu (BCICTS, 2022)