A runtime adaptive controller for supporting hardware components with variable latency. - Christian Pilato; Vito Giovanni Castellana; Silvia Lovergine; Fabrizio Ferrandi (AHS, 2011)

Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators. - Vito Giovanni Castellana; Fabrizio Ferrandi (SC Companion, 2012)

Accelerating semantic graph databases on commodity clusters. - Alessandro Morari; Vito Giovanni Castellana; David Haglin; John Feo; Jesse Weaver; Antonino Tumeo; Oreste Villa (IEEE BigData, 2013)

Scheduling independent liveness analysis for register binding in high level synthesis. - Vito Giovanni Castellana; Fabrizio Ferrandi (DATE, 2013)

An automated flow for the High Level Synthesis of coarse grained parallel applications. - Vito Giovanni Castellana; Fabrizio Ferrandi (FPT, 2013)

Applications Acceleration through Adaptive Hardware Components. - Vito Giovanni Castellana; Fabrizio Ferrandi (IPDPS Workshops, 2013)

Composing Data Parallel Code for a SPARQL Graph Engine. - Vito Giovanni Castellana; Antonino Tumeo; Oreste Villa; David Haglin; John Feo (SocialCom, 2013)

An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems. - Vito Giovanni Castellana; Antonino Tumeo; Fabrizio Ferrandi (DATE, 2014)

High-level synthesis of memory bound and irregular parallel applications with Bambu. - Vito Giovanni Castellana; Antonino Tumeo; Fabrizio Ferrandi (Hot Chips Symposium, 2014)

Scaling Semantic Graph Databases in Size and Performance. - Alessandro Morari; Vito Giovanni Castellana; Oreste Villa; Antonino Tumeo; Jesse Weaver; David Haglin; Sutanay Choudhury; John Feo (IEEE Micro, 2014)

Toward a data scalable solution for facilitating discovery of science resources. - Jesse Weaver; Vito Giovanni Castellana; Alessandro Morari; Antonino Tumeo; Sumit Purohit; Alan R. Chappell; David Haglin; Oreste Villa; Sutanay Choudhury; Karen Schuchardt; John Feo (Parallel Comput., 2014)

C-based high level synthesis of parallel applications targeting adaptive hardware components. - Vito Giovanni Castellana (2014)

GEMS: Graph Database Engine for Multithreaded Systems. - Alessandro Morari; Vito Giovanni Castellana; Oreste Villa; Jesse Weaver; Gregory Todd Williams; David J. Haglin; Antonino Tumeo; John Feo (Big Data - Algorithms, Analytics, and Applications, 2015)

High-Performance, Distributed Dictionary Encoding of RDF Datasets. - Alessandro Morari; Jesse Weaver; Oreste Villa; David J. Haglin; Antonino Tumeo; Vito Giovanni Castellana; John Feo (CLUSTER, 2015)

Function Proxies for Improved Resource Sharing in High Level Synthesis. - Marco Minutoli; Vito Giovanni Castellana; Antonino Tumeo; Fabrizio Ferrandi (FCCM, 2015)

Inter-procedural resource sharing in High Level Synthesis through function proxies. - Marco Minutoli; Vito Giovanni Castellana; Antonino Tumeo; Fabrizio Ferrandi (FPL, 2015)

High Level Synthesis of RDF Queries for Graph Analytics. - Vito Giovanni Castellana; Marco Minutoli; Alessandro Morari; Antonino Tumeo; Marco Lattuada 001; Fabrizio Ferrandi (ICCAD, 2015)

A visual analytics paradigm enabling trillion-edge graph exploration. - Pak Chung Wong; David J. Haglin; David Gillen; Daniel G. Chavarría-Miranda; Vito Giovanni Castellana; Cliff A. Joslyn; Alan R. Chappell; Song Zhang 004 (LDAV, 2015)

In-Memory Graph Databases for Web-Scale Data. - Vito Giovanni Castellana; Alessandro Morari; Jesse Weaver; Antonino Tumeo; David Haglin; Oreste Villa; John Feo (Computer, 2015)

Enabling the high level synthesis of data analytics accelerators. - Marco Minutoli; Vito Giovanni Castellana; Antonino Tumeo; Marco Lattuada 001; Fabrizio Ferrandi (CODES+ISSS, 2016)

A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries. - Marco Minutoli; Vito Giovanni Castellana; Antonino Tumeo; Fabrizio Ferrandi; Marco Lattuada 001 (FCCM, 2016)

A dynamically scheduled architecture for the synthesis of graph methods. - Marco Minutoli; Vito Giovanni Castellana; Antonino Tumeo; Marco Lattuada 001; Fabrizio Ferrandi (Hot Chips Symposium, 2016)

Efficient synthesis of graph methods: a dynamically scheduled architecture. - Marco Minutoli; Vito Giovanni Castellana; Antonino Tumeo; Marco Lattuada 001; Fabrizio Ferrandi (ICCAD, 2016)

GraQL: A Query Language for High-Performance Attributed Graph Databases. - Daniel G. Chavarría-Miranda; Vito Giovanni Castellana; Alessandro Morari; David Haglin; John Feo (IPDPS Workshops, 2016)

High-Performance Data Analytics Beyond the Relational and Graph Data Models with GEMS. - Vito Giovanni Castellana; Marco Minutoli; Shreyansh Bhatt; Khushbu Agarwal; Arthur Bleeker; John Feo; Daniel G. Chavarría-Miranda; David J. Haglin (IPDPS Workshops, 2017)

SHAD: The Scalable High-Performance Algorithms and Data-Structures Library. - Vito Giovanni Castellana; Marco Minutoli (CCGrid, 2018)

Software defined architectures for data analytics. - Vito Giovanni Castellana; Marco Minutoli; Antonino Tumeo; Marco Lattuada 001; Pietro Fezzardi; Fabrizio Ferrandi (ASP-DAC, 2019)

A Parallel Graph Environment for Real-World Data Analytics Workflows. - Vito Giovanni Castellana; Maurizio Drocco; John Feo; Jesun Sahariar Firoz; Thejaka Amila Kanewala; Andrew Lumsdaine; Joseph B. Manzano; Andres Marquez 001; Marco Minutoli; Joshua Suetterlein; Antonino Tumeo; Marcin Zalewski (DATE, 2019)

Invited: Software Defined Accelerators From Learning Tools Environment. - Antonino Tumeo; Marco Minutoli; Vito Giovanni Castellana; Joseph B. Manzano; Vinay Amatya; David Brooks 001; Gu-Yeon Wei (DAC, 2020)

Practical Distributed Programming in C++. - Maurizio Drocco; Vito Giovanni Castellana; Marco Minutoli (HPDC, 2020)

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators. - Marco Minutoli; Vito Giovanni Castellana; Cheng Tan 002; Joseph B. Manzano; Vinay Amatya; Antonino Tumeo; David Brooks 001; Gu-Yeon Wei (ICCAD, 2020)

OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays. - Cheng Tan 002; Nicolas Bohm Agostini; Jeff Zhang 001; Marco Minutoli; Vito Giovanni Castellana; Chenhao Xie 001; Tong Geng; Ang Li 006; Kevin J. Barker; Antonino Tumeo (ASAP, 2021)

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis. - Jeff Jun Zhang; Nicolas Bohm Agostini; Shihao Song; Cheng Tan 002; Ankur Limaye; Vinay Amatya; Joseph B. Manzano; Marco Minutoli; Vito Giovanni Castellana; Antonino Tumeo; Gu-Yeon Wei; David Brooks 001 (ASAP, 2021)

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications. - Fabrizio Ferrandi; Vito Giovanni Castellana; Serena Curzel; Pietro Fezzardi; Michele Fiorito; Marco Lattuada 001; Marco Minutoli; Christian Pilato; Antonino Tumeo (DAC, 2021)

Productive Programming of Distributed Systems with the SHAD C++ Library. - Vito Giovanni Castellana; Marco Minutoli (HPDC, 2021)

Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators. - Serena Curzel; Nicolas Bohm Agostini; Shihao Song; Ismet Dagli; Ankur Limaye; Cheng Tan 002; Marco Minutoli; Vito Giovanni Castellana; Vinay Amatya; Joseph B. Manzano; Anup Das 001; Fabrizio Ferrandi; et al. (ICCAD, 2021)

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers. - Vito Giovanni Castellana; Antonino Tumeo; Fabrizio Ferrandi (IPDPS, 2021)

Towards superior software portability with SHAD and HPX C++ libraries. - Nanmiao Wu; Vito Giovanni Castellana; Hartmut Kaiser (CF, 2022)

The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invited. - Nicolas Bohm Agostini; Serena Curzel; Ankur Limaye; Vinay Amatya; Marco Minutoli; Vito Giovanni Castellana; Joseph B. Manzano; Antonino Tumeo; Fabrizio Ferrandi (DAC, 2022)

SO(DA)2: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk). - Antonino Tumeo; Nicolas Bohm Agostini; Serena Curzel; Ankur Limaye; Cheng Tan 002; Vinay Amatya; Marco Minutoli; Vito Giovanni Castellana; Ang Li 006; Joseph B. Manzano (PARMA-DITAM@HiPEAC, 2022)

From High-Level Frameworks to custom Silicon with SODA. - Serena Curzel; Nicolas Bohm Agostini; Reece Neff; Ankur Limaye; Jeff Jun Zhang; Vinay Amatya; Marco Minutoli; Vito Giovanni Castellana; Joseph B. Manzano; David Brooks 001; Gu-Yeon Wei; Fabrizio Ferrandi; et al. (HCS, 2022)

An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration. - Nicolas Bohm Agostini; Serena Curzel; Vinay Amatya; Cheng Tan 002; Marco Minutoli; Vito Giovanni Castellana; Joseph B. Manzano; David R. Kaeli; Antonino Tumeo (ICCAD, 2022)

SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon. - Nicolas Bohm Agostini; Ankur Limaye; Marco Minutoli; Vito Giovanni Castellana; Joseph B. Manzano; Antonino Tumeo; Serena Curzel; Fabrizio Ferrandi (ICCAD, 2022)

Bridging Python to Silicon: The SODA Toolchain. - Nicolas Bohm Agostini; Serena Curzel; Jeff Jun Zhang; Ankur Limaye; Cheng Tan 002; Vinay Amatya; Marco Minutoli; Vito Giovanni Castellana; Joseph B. Manzano; David Brooks 001; Gu-Yeon Wei; Antonino Tumeo (IEEE Micro, 2022)

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators. - Serena Curzel; Nicolas Bohm Agostini; Vito Giovanni Castellana; Marco Minutoli; Ankur Limaye; Joseph B. Manzano; Jeff Zhang 001; David Brooks 001; Gu-Yeon Wei; Fabrizio Ferrandi; Antonino Tumeo (IEEE Trans. Computers, 2022)

Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics. - Marco Minutoli; Vito Giovanni Castellana; Nicola Saporetti; Stefano Devecchi; Marco Lattuada 001; Pietro Fezzardi; Antonino Tumeo; Fabrizio Ferrandi (IEEE Trans. Computers, 2022)

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis. - Vito Giovanni Castellana; Nicolas Bohm Agostini; Ankur Limaye; Vinay Amatya; Marco Minutoli; Joseph B. Manzano; Antonino Tumeo; Serena Curzel; Michele Fiorito; Fabrizio Ferrandi (ASP-DAC, 2023)

Towards Automated Generation of Chiplet-Based Systems Invited Paper. - Ankur Limaye; Claudio Barone; Nicolas Bohm Agostini; Marco Minutoli; Joseph B. Manzano; Vito Giovanni Castellana; Giovanni Gozzi; Michele Fiorito; Serena Curzel; Fabrizio Ferrandi; Antonino Tumeo (ASPDAC, 2024)

Custom Accessors: Enabling Scalable Data Ingestion, (Re-)Organization, and Analysis on Distributed Systems. - Vito Giovanni Castellana; Burcu O. Mutlu; Ian Di Dio Lavore; Jesun Firoz; Katherine E. Wolf; Marco Minutoli; John Feo (IEEE Big Data, 2024)

Extending High-Level Synthesis with AI/ML Methods. - Nicolas Bohm Agostini; Giovanni Gozzi; Michele Fiorito; Claudio Barone; Serena Curzel; Ankur Limaye; Marco Minutoli; Vito Giovanni Castellana; Joseph B. Manzano; Fabrizio Ferrandi; Antonino Tumeo (ICCAD, 2024)

To Cache or not to Cache? Exploring the Design Space of Tunable, HLS-generated Accelerators. - Claudio Barone; Rishika Kushwah; Ankur Limaye; Vito Giovanni Castellana; Giovanni Gozzi; Michele Fiorito; Fabrizio Ferrandi; Antonino Tumeo (MEMSYS, 2024)

Programming the Future: the Essential Role of System Topology Awareness in Heterogeneous Disaggregated Environments. - Beatrice Branchini; Ian Di Dio Lavore; Vito Giovanni Castellana; Marco D. Santambrogio (MEMSYS, 2024)

Exploring Architectural-Aware Affinity Policies in Modern HPC Runtimes. - Ian Di Dio Lavore; Vito Giovanni Castellana; John Feo; Marco D. Santambrogio (PEARC, 2024)

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems. - Ankur Limaye; Nicolas Bohm Agostini; Claudio Barone; Vito Giovanni Castellana; Michele Fiorito; Fabrizio Ferrandi; Andres Marquez 001; Antonino Tumeo (ASP-DAC, 2025)

SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators. - Giovanni Gozzi; Michele Fiorito; Serena Curzel; Claudio Barone; Vito Giovanni Castellana; Marco Minutoli; Antonino Tumeo; Fabrizio Ferrandi (ACM Trans. Reconfigurable Technol. Syst., 2025)