A Novel Sizing Method Aiming Security Against Differential Power Analysis. - Vitor G. Lima; Plinio Finkenauer; Vinícius V. Camargo; Felipe S. Marques 001; Leomar R. Junior; Rafael Iankowski Soares (ICECS, 2018)

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. - Vitor G. Lima; Guilherme Paim; Leandro M. G. Rocha; Leomar S. da Rosa Jr.; Felipe S. Marques 001; Eduardo A. C. da Costa; Vinícius V. Camargo; Rafael Soares; Sergio Bampi (ISCAS, 2019)

Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS. - Rodrigo N. Wuerdig; Vitor G. Lima; Filipe D. Baumgratz; Rafael Soares; Sergio Bampi (LASCAS, 2020)

Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture. - Mateus Terribele Leme; Guilherme Paim; Leandro M. G. Rocha; Patrícia Ücker; Vitor G. Lima; Rafael Soares; Eduardo A. C. da Costa; Sergio Bampi (MWSCAS, 2020)