From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. - Ney Laert Vilar Calazans; Edson I. Moreno; Fabiano Hessel; Vitor M. da Rosa; Fernando Moraes 001; Everton Carara (SBCCI, 2003)

Abstract RTOS Modeling for Embedded Systems. - Fabiano Hessel; Vitor M. da Rosa; Igor M. Reis; Ricardo Planner; César A. M. Marcon; Altamiro Amadeu Susin (IEEE International Workshop on Rapid System Prototyping, 2004)

Scheduling refinement in abstract RTOS models. - Fabiano Hessel; Vitor M. da Rosa; Carlos Eduardo Reif; César A. M. Marcon; Tatiana Gadelha Serra dos Santos (ACM Trans. Embed. Comput. Syst., 2006)