A Proposal to Expand the Community of Users Able to Process Historical Rainfall Data by Means of the Today Available Open Source Libraries. - Paolino Di Felice; Luca Finocchio; Daniele Leombruni; Vittoriano Muttillo (J. Comput. Inf. Technol., 2014)

Hardware performance sniffers for embedded systems profiling. - Andrea Moro; Fabio Federici; Giacomo Valente; Luigi Pomante; Marco Faccio; Vittoriano Muttillo (WISES, 2015)

A Flexible Profiling Sub-System for Reconfigurable Logic Architectures. - Giacomo Valente; Vittoriano Muttillo; Luigi Pomante; Fabio Federici; Marco Faccio; Andrea Moro; Serenella Ferri; Carlo Tieri (PDP, 2016)

Design and validation of multi-core embedded systems under time-to-prototype and high performance constraints. - Marco Faccio; Fabio Federici; Giuseppe Marini; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (RTSI, 2016)

A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system. - Vittoriano Muttillo; Giacomo Valente; Fabio Federici; Luigi Pomante; Marco Faccio; Carlo Tieri; Serenella Ferri (EURASIP J. Embed. Syst., 2016)

Simulation-Based Analysis of a Hardware Mechanism to Support Isolation in Mixed-Criticality Network on Chip. - Fabio Federici; Mattia Micozzi; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (EMS, 2017)

An Efficient Performance-Driven Approach for HW/SW Co-Design. - Daniele Di Pompeo; Emilio Incerto; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (ICPE, 2017)

Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems. - Giacomo Valente; Marco Rotondi; Vittoriano Muttillo (ICPE, 2017)

Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante (DSD, 2018)

Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante (PARMA-DITAM@HiPEAC, 2018)

HEPSIM: An ESL HW/SW co-simulator/analysis tool for heterogeneous parallel embedded systems. - Daniele Ciambrone; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (MECO, 2018)

Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements. - Vittoriano Muttillo; Giacomo Valente (MECO, 2018)

HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology. - Vittoriano Muttillo; Giacomo Valente; Daniele Ciambrone; Vincenzo Stoico; Luigi Pomante (RAPIDO, 2018)

Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante (ICPE Companion, 2018)

CC4CS: an Off-the-Shelf Unifying Statement-Level Performance Metric for HW/SW Technologies. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante; Vincenzo Stoico; Fausto D'Antonio; Fabio Salice (ICPE Companion, 2018)

HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions. - Vittoriano Muttillo; Luigi Pomante; Patricia Balbastre; José E. Simó; Alfons Crespo (DSD, 2019)

J4CS: An Early-Stage Statement-Level Metric for Energy Consumption of Embedded SW. - Vittoriano Muttillo (MECO, 2019)

The AQUAS ECSEL Project Aggregated Quality Assurance for Systems: Co-Engineering Inside and Across the Product Life Cycle. - Luigi Pomante; Vittoriano Muttillo; Bohuslav Krena; Tomás Vojnar; Filip Veljkovic; Pacome Magnin; Martin Matschnig; Bernhard Fischer; Jabier Martinez; Thomas Gruber 004 (Microprocess. Microsystems, 2019)

HW/SW co-design methodology and framework for mixed-criticality and real-time embedded systems. - Vittoriano Muttillo (2019)

Benchmarking Analysis and Characterization of Hypervisors for Space Multicore Systems. - Vittoriano Muttillo; Luca Tiberi; Luigi Pomante; Paolo Serri (J. Aerosp. Inf. Syst., 2019)

Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante; Hector Posadas; Javier Merino; Eugenio Villar (DSD, 2020)

An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems. - Vittoriano Muttillo; Paolo Giammatteo; Giuseppe Fiorilli; Luigi Pomante (PARMA-DITAM@HiPEAC, 2020)

A Low Cost and Flexible Power Line Communication Sensory System for Home Automation. - Mirco Muttillo; Vittoriano Muttillo; Luigi Pomante; Leonardo Pantoli (MetroInd4.0&IoT, 2020)

Towards the Design of Microcontroller Based Embedded Sensory systems with a Five-Parameter Single Diode Estimation Method for Photovoltaic Panels. - Mirco Muttillo; Vittoriano Muttillo; Tullio de Rubeis (MetroInd4.0&IoT, 2020)

An early-stage statement-level metric for energy characterization of embedded processors. - Vittoriano Muttillo; Paolo Giammatteo; Vincenzo Stoico; Luigi Pomante (Microprocess. Microsystems, 2020)

SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems. - Luigi Pomante; Vittoriano Muttillo; Marco Santic; Paolo Serri (Microprocess. Microsystems, 2020)

Model-Based HW/SW Co-Design Methodology for UAV Systems Development. - Vittoriano Muttillo; Vincenzo Stoico (MECO, 2021)

Statement-Level Timing Estimation for Embedded System Design Using Machine Learning Techniques. - Vittoriano Muttillo; Paolo Giammatteo; Vincenzo Stoico (ICPE, 2021)

AIDOaRt: AI-augmented Automation for DevOps, a model-based framework for continuous development in Cyber-Physical Systems. - Hugo Bruneliere; Vittoriano Muttillo; Romina Eramo; Luca Berardinelli; Abel Gómez 001; Alessandra Bagnato; Andrey Sadovykh; Antonio Cicchetti (Microprocess. Microsystems, 2022)

SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design. - Vittoriano Muttillo; Luigi Pomante; Marco Santic; Giacomo Valente (Comput. Electr. Eng., 2023)

SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations. - Vittoriano Muttillo; Vincenzo Stoico; Marco Santic; Giacomo Valente; Luigi Pomante; Daniele Frigioni (ICCD, 2024)

Towards Synthetic Trace Generation of Modeling Operations using In-Context Learning Approach. - Vittoriano Muttillo; Claudio Di Sipio; Riccardo Rubei; Luca Berardinelli; MohammadHadi Dehghani (ASE, 2024)

Experiences and challenges from developing cyber-physical systems in industry-academia collaboration. - Johan Cederbladh; Romina Eramo; Vittoriano Muttillo; Per Erik Strandberg (Softw. Pract. Exp., 2024)

Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection. - Giacomo Valente; Vittoriano Muttillo; Fabio Federici; Luigi Pomante; Tania Di Mascio (IEEE Embed. Syst. Lett., 2024)

Multi-Partner Project: A Model-Driven Engineering Framework for Federated Digital Twins of Industrial Systems (MATISSE). - Alessio Bucaioni; Romina Eramo; Luca Berardinelli; Hugo Bruneliere; Benoît Combemale; Djamel Eddine Khelladi; Vittoriano Muttillo; Andrey Sadovykh; Manuel Wimmer (DATE, 2025)

System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. - Vittoriano Muttillo; Vincenzo Stoico; Giacomo Valente; Marco Santic; Luigi Pomante; Daniele Frigioni (PARMA-DITAM, 2025)

Leveraging synthetic trace generation of modeling operations for intelligent modeling assistants using large language models. - Vittoriano Muttillo; Claudio Di Sipio; Riccardo Rubei; Luca Berardinelli (Inf. Softw. Technol., 2025)

SLIDE-x (System-Level Infrastructure for HW/SW Dataset E-xtraction). - Vittoriano Muttillo; Vincenzo Stoico (DROPS Artifacts, 2025)