A low-power concurrent multiplier-accumulator using conditional evaluation. - V. A. Bartlett; Eckhard Grass (ICECS, 1999)

A Low-Power Asynchronous VLSI FIR Filter. - V. A. Bartlett; Eckhard Grass (ARVLSI, 2001)

Using carry-save adders in low-power multiplier blocks. - Viv A. Bartlett; Andrew G. Dempster (ISCAS (4), 2001)

Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic. - V. A. Bartlett; Eckhard Grass (VLSI Design, 2001)

Energy efficiency of 2-step charging power-clock for adiabatic logic. - Himadri Singh Raghav; Vivian A. Bartlett; Izzet Kale (PATMOS, 2016)

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (ECCTD, 2017)

A novel power analysis attack resilient adiabatic logic without charge sharing. - Himadri Singh Raghav; Vivian A. Bartlett; Izzet Kale (ECCTD, 2017)

Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations. - Himadri Singh Raghav; Vivian A. Bartlett; Izzet Kale (PATMOS, 2017)

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (PATMOS, 2018)

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications. - Himadri Singh Raghav; Vivian A. Bartlett; Izzet Kale (PATMOS, 2018)

Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (Integr., 2018)

Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations. - Himadri Singh Raghav; Vivian A. Bartlett; Izzet Kale (Microelectron. J., 2018)

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. - Sachin Maheshwari; Vivian A. Bartlett; Izzet Kale (Integr., 2019)

Investigating the influence of adiabatic load on the 4-phase adiabatic system design. - Himadri Singh Raghav; V. A. Bartlett (Integr., 2020)

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits. - Sachin Maheshwari; Viv A. Bartlett; Izzet Kale (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)