Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. - Vivek Asthana; Malathi Kar; Jean Jimenez; Jean-Philippe Noel; Sébastien Haendler; Philippe Galy (ESSCIRC, 2013)

6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. - Vivek Asthana; Malathi Kar; Jean Jimenez; Sébastien Haendler; Philippe Galy (ICICDT, 2013)

Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. - Parmanand Singh; Vivek Asthana; Radhakrishnan Sithanandam; Anand Bulusu; Sudeb Dasgupta (VLSID, 2014)

0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications. - Vivek Asthana; M. Jagadesh Kumar; Ayush Kulshrestha; Munish Kumar; Saikat Kumar Banik; Shruti Aggarwal (ISCAS, 2020)

5GHz SRAM for High-Performance Compute Platform in 5nm CMOS. - R. Mathur; M. Kumar; Vivek Asthana; S. Aggarwal; S. Gupta; D. Wanjul; A. Baradia; S. Thota; P. Jain; B. Zheng; A. Cubeta; S. Thyagarajan; et al. (CICC, 2022)