An optimization based approach to the partial scan design problem. - Vivek Chickermane; Janak H. Patel (ITC, 1990)

Restructuring VLSI layout representations for efficiency. - Ravi Nair; Vivek Chickermane; Ray Chamberlain (EURO-DAC, 1991)

A Fault Oriented Partial Scan Design Approach. - Vivek Chickermane; Janak H. Patel (ICCAD, 1991)

APT: An Area-Performance-Testability Driven Placement Algorithm. - Sungho Kim; Prithviraj Banerjee; Vivek Chickermane; Janak H. Patel (DAC, 1992)

A comparative study of design for testability methods using high-level and gate-level descriptions. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (ICCAD, 1992)

Design for Testability Using Architectural Descriptions. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (ITC, 1992)

Probe point insertion for at-speed test. - Elizabeth M. Rudnick; Vivek Chickermane; Janak H. Patel (VTS, 1992)

Non-Scan Design-for-Testability Techniques for Sequential Circuits. - Vivek Chickermane; Elizabeth M. Rudnick; Prithviraj Banerjee; Janak H. Patel (DAC, 1993)

Impact of high level functional constraints on testability. - Jaushin Lee; Vivek Chickermane; Janak H. Patel (VTS, 1993)

Addressing design for testability at the architectural level. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

An observability enhancement approach for improved testability and at-speed test. - Elizabeth M. Rudnick; Vivek Chickermane; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Sequential circuit testability enhancement using a nonscan approach. - Elizabeth M. Rudnick; Vivek Chickermane; Prithviraj Banerjee; Janak H. Patel (IEEE Trans. Very Large Scale Integr. Syst., 1995)

A Design For Test Perspective on I/O Management. - Kamran Zarrineh; Vivek Chickermane; Gareth Nicholls; Mike Palmer (ICCD, 1996)

Addressing Early Design-For-Test Synthesis in a Production Environment. - Vivek Chickermane; Kamran Zarrineh (ITC, 1997)

Integrating Logic BIST in VLSI Designs with Embedded Memories. - Vivek Chickermane; Scott Richter; Carl Barnhart (VTS, 2000)

A building block BIST methodology for SOC designs: a case study. - Patrick R. Gallagher Jr.; Vivek Chickermane; Steven Gregor; Thomas S. Pierre (ITC, 2001)

System-on-Chip Testability Using LSSD Scan Structures. - Kamran Zarrineh; Shambhu J. Upadhyaya; Vivek Chickermane (IEEE Des. Test Comput., 2001)

Channel Masking Synthesis for Efficient On-Chip Test Compression. - Vivek Chickermane; Brian Foutz; Brion L. Keller (ITC, 2004)

An Economic Analysis and ROI Model for Nanometer Test. - Brion L. Keller; Mick Tegethoff; Thomas Bartenstein; Vivek Chickermane (ITC, 2004)

Practical Aspects of Delay Testing for Nanometer Chips. - Vivek Chickermane; Brion L. Keller; Kevin McCauley; Anis Uzzaman (Asian Test Symposium, 2005)

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. - Hiroyuki Nakamura; Akio Shirokane; Yoshihito Nishizaki; Anis Uzzaman; Vivek Chickermane; Brion L. Keller; Tsutomu Ube; Yoshihiko Terauchi (Asian Test Symposium, 2005)

Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology. - Brian Foutz; Vivek Chickermane; Bing Li; Harry Linzer; Gary Kunselman (ATS, 2006)

Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. - Sanae Seike; Ken Namura; Yukio Ohya; Anis Uzzaman; Shinichi Arima; Dale Meehl; Vivek Chickermane; Azumi Kobayashi; Satoshi Tanaka; Hiroyuki Adachi (ATS, 2006)

A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. - Anis Uzzaman; Brion L. Keller; Vivek Chickermane (ATS, 2006)

Low Power Reduced Pin Count Test Methodology. - Krishna Chakravadhanula; Nitin Parimi; Brian Foutz; Bing Li; Vivek Chickermane (ATS, 2007)

Test Generation for State Retention Logic. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Steven Gregor (ATS, 2008)

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. - Vivek Chickermane; Patrick R. Gallagher Jr.; James Sage; Paul Yuan; Krishna Chakravadhanula (ITC, 2008)

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Anis Uzzaman (Asian Test Symposium, 2009)

Capture power reduction using clock gating aware test generation. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Prashant Narang (ITC, 2009)

Automating IEEE 1500 Core Test—An EDA Perspective. - Krishna Chakravadhanula; Vivek Chickermane (IEEE Des. Test Comput., 2009)

Low cost at-speed testing using On-Product Clock Generation compatible with test compression. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; R. Malneedi; Thomas J. Snethen; Vikram Iyengar; David E. Lackey; Gary Grise (ITC, 2010)

Automation of 3D-DfT Insertion. - Sergej Deutsch; Vivek Chickermane; Brion L. Keller; Subhasish Mukherjee; Mario Konijnenburg; Erik Jan Marinissen; Sandeep Kumar Goel (Asian Test Symposium, 2011)

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. - Sergej Deutsch; Brion L. Keller; Vivek Chickermane; Subhasish Mukherjee; Navdeep Sood; Sandeep Kumar Goel; Ji-Jan Chen; Ashok Mehta; Frank Lee 004; Erik Jan Marinissen (ITC, 2012)

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. - Christos Papameletis; Brion L. Keller; Vivek Chickermane; Erik Jan Marinissen; Said Hamdioui (ETS, 2013)

SmartScan - Hierarchical test compression for pin-limited low power designs. - Krishna Chakravadhanula; Vivek Chickermane; Don Pearl; Akhil Garg 001; R. Khurana; Subhasish Mukherjee; P. Nagaraj (ITC, 2013)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)

Efficient testing of hierarchical core-based SOCs. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; Akhil Garg 001; Richard Schoonover; James Sage; Don Pearl; Thomas J. Snethen (ITC, 2014)

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. - Srivaths Ravi 001; Vivek Chickermane; Krishna Chakravadhanula (VLSID, 2014)

Innovative practices session 1C: Existing/emerging low power techniques. - Charutosh Dixit; Ramesh C. Tekumalla; Wei Zhao; Nilanjan Mukherjee 001; Vivek Chickermane (VTS, 2014)

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. - Konstantin Shibin; Vivek Chickermane; Brion L. Keller; Christos Papameletis; Erik Jan Marinissen (ATS, 2015)

A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. - Sameer Chillarige; S. Virdi; Anil Malik; Krishna Chakravadhanula; Vivek Chickermane; Joe Swenton; G. Vandling (NATW, 2015)

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. - Christos Papameletis; Brion L. Keller; Vivek Chickermane; Said Hamdioui; Erik Jan Marinissen (IEEE Des. Test, 2015)

Advancing test compression to the physical dimension. - Krishna Chakravadhanula; Vivek Chickermane; Paul Cunningham; Brian Foutz; Dale Meehl; Louis Milano; Christos Papameletis; David Scott; Steev Wilcox (ITC, 2017)

Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. - Christos Papameletis; Vivek Chickermane; Brian Foutz; Sarthak Singhal; Krishna Chakravadhanula (ITC, 2019)

Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. - Irith Pomeranz; Vivek Chickermane; Srikanth Venkataraman (VTS, 2019)

Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium. - Stefano Di Carlo; Peilin Song; Vivek Chickermane (IEEE Des. Test, 2020)

PPA Optimization of Test Points in Automotive Designs. - Brian Foutz; Sarthak Singhal; Prateek Kumar Rai; Krishna Chakravadhanula; Vivek Chickermane; Bharath Nandakumar; Sameer Chillarige; Christos Papameletis; Satish Ravichandran (ITC, 2022)

The Future of Design for Test and Silicon Lifecycle Management. - Janusz Rajski; Vivek Chickermane; Jean-François Côté; Stephan Eggersglüß; Nilanjan Mukherjee 001; Jerzy Tyszer (IEEE Des. Test, 2024)