Virtual Multi-Antenna Array for Estimating the Angle-of-Arrival of a RF Transmitter. - François Quitin; Vivek Govindaraj; Xionghu Zhong; Wee-Peng Tay (VTC Fall, 2016)

DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. - Vivek Govindaraj; Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (APCCAS, 2019)

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Zhong Gao; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (ISSCC, 2020)

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. - Jianglin Du; Teerachot Siriburanon; Xi Chen 070; Yizhe Hu; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (VLSI Circuits, 2021)

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. - Jianglin Du; Teerachot Siriburanon; Yizhe Hu; Vivek Govindaraj; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2021)

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)