Logic SER Reduction through Flipflop Redesign. - Vivek Joshi; Rajeev R. Rao; David T. Blaauw; Dennis Sylvester (ISQED, 2006)

Soft-edge flip-flops for improved timing yield: design and optimization. - Vivek Joshi; David T. Blaauw; Dennis Sylvester (ICCAD, 2007)

Leakage power reduction using stress-enhanced layouts. - Vivek Joshi; Brian Cline; Dennis Sylvester; David T. Blaauw; Kanak Agarwal 001 (DAC, 2008)

STEEL: a technique for stress-enhanced standard cell library design. - Brian Cline; Vivek Joshi; Dennis Sylvester; David T. Blaauw (ICCAD, 2008)

Stress aware layout optimization. - Vivek Joshi; Brian Cline; Dennis Sylvester; David T. Blaauw; Kanak Agarwal 001 (ISPD, 2008)

IUF Scheduling Algorithm for Improving the Schedulability, Predictability and Sustainability of the Real Time System. - Radhakrishna Naik; Vivek Joshi; Ramchandra R. Manthalkar (ICETET, 2009)

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic. - Rajeev R. Rao; Vivek Joshi; David T. Blaauw; Dennis Sylvester (ACM Trans. Design Autom. Electr. Syst., 2009)

Analyzing electrical effects of RTA-driven local anneal temperature variation. - Vivek Joshi; Kanak Agarwal 001; Dennis Sylvester; David T. Blaauw (ASP-DAC, 2010)

Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS. - Vivek Joshi; Michael Wieckowski; Gregory K. Chen; David T. Blaauw; Dennis Sylvester (CICC, 2010)

Closed-form modeling of layout-dependent mechanical stress. - Vivek Joshi; Valeriy Sukharev; Andres Torres; Kanak Agarwal 001; Dennis Sylvester; David T. Blaauw (DAC, 2010)

Analysis and optimization of SRAM robustness for double patterning lithography. - Vivek Joshi; Kanak Agarwal 001; David T. Blaauw; Dennis Sylvester (ICCAD, 2010)

Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. - Vivek Joshi; Kanak Agarwal 001; Dennis Sylvester (ISQED, 2010)

Mechanical Stress Aware Optimization for Leakage Power Reduction. - Vivek Joshi; Brian Cline; Dennis Sylvester; David T. Blaauw; Kanak Agarwal 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Empirical Investigation of Radiologists' Priorities for PACS Selection: An Analytical Hierarchy Process Approach. - Vivek Joshi; Kyootai Lee; David Melson; Vamsi R. Narra (J. Digit. Imaging, 2011)

Design-patterning co-optimization of SRAM robustness for double patterning lithography. - Vivek Joshi; Kanak Agarwal 001; Dennis Sylvester (ASP-DAC, 2012)

SRAM read current variability and its dependence on transistor statistics. - Sriramkumar Venugopalan; Vivek Joshi; Luis Zamudio; Matthias Goldbach; Gert Burbach; Ralf Van Bentum; Sriram Balasubramanian (CICC, 2013)

HTOL SRAM Vmin shift considerations in scaled HKMG technologies. - S. Balasubramanian; Vivek Joshi; Torsten Klick; Randy W. Mann; Joseph Versaggi; Akhilesh Gautam; C. Weintraub; G. Kurz; G. Krause; Andreas Kerber; Biju Parameshwaran; Tanya Nigam (CICC, 2014)

PACS Administrators' and Radiologists' Perspective on the Importance of Features for PACS Selection. - Vivek Joshi; Vamsi R. Narra; Kailash Joshi; Kyootai Lee; David Melson (J. Digit. Imaging, 2014)

SRAM Vmax stability considerations. - David Burnett; Sriram Balasubramanian; Vivek Joshi; Sanjay Parihar; Jack M. Higman; C. Weintraub (IRPS, 2015)

Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing. - Yoann Mamy Randriamihaja; William McMahon; S. Balasubramanian; Tanya Nigam; Biju Parameshwaran; Randy W. Mann; Torsten Klick; T. Schaefer; A. Kumar; Y. Song; Vivek Joshi; Rakesh Ranjan; et al. (IRPS, 2015)

Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications. - Sriram Balasubramanian; Ninad Pimparkar; Mangesh Kushare; Vinayak Mahajan; Juhi Bansal; Takashi Shimizu; Vivek Joshi; Kun Qian; Arunima Dasgupta; Karthik Chandrasekaran; Chad Weintraub; Ali Icel (ISQED, 2016)

Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT Application. - Mingcheng Chang; Nigel Chan; Vivek Joshi; Sandra Hecker; Udo Ziller; Petra Poth; Alban Zaka; Tom Herrmann; Seunghwan Seo; Hongsik Yoon; Xin Zou; Zhen Xu; et al. (ESSDERC, 2018)

MRI-based active shape model of the human proximal femur using fiducial and secondary landmarks and its validation. - Xiaoliu Zhang; Cheng Chen 016; Sean Boone; Vivek Joshi; Arakua Welbeck; Guoyuan Liang; Gregory Chang; Punam K. Saha (Biomedical Applications in Molecular, Structural, and Functional Imaging, 2018)

10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application. - Motoi Ichihashi; Youngtag Woo; Muhammed Ahosan Ul Karim; Vivek Joshi; David Burnett (SoCC, 2018)

Towards enhanced accountability in complying with healthcare regulations. - Preethu Rose Anish; Vivek Joshi; Abhishek Sainani; Smita Ghaisas (SEH@ICSE, 2019)

Simulation Based Assessment of SRAM Data Retention Voltage. - Zhipeng Dong; Xi Cao; M. Ahosan Ul Karim; Vivek Joshi; Torsten Klick; Joerg Schmid (ISQED, 2019)

Extracting and Classifying Requirements from Software Engineering Contracts. - Abhishek Sainani; Preethu Rose Anish; Vivek Joshi; Smita Ghaisas (RE, 2020)

Writaupair: Assistive Platform for Children with Writing Difficulties. - Preethu Rose Anish; Vivek Joshi; Pratik Sonar; Smita Ghaisas (IRI, 2021)

Domain adaptation for an automated classification of deontic modalities in software engineering contracts. - Vivek Joshi; Preethu Rose Anish; Smita Ghaisas (ESEC/SIGSOFT FSE, 2021)

Automated Labeling and Classification of Business Rules from Software Requirement Specifications. - Preethu Rose Anish; Prashant Lawhatre; Ranit Chatterjee; Vivek Joshi; Smita Ghaisas (ICSE (SEIP), 2022)

Efficient and Scalable Place and Route Methodology for Large-Scale Hierarchical Designs: Achieving Faster Turnaround Time and Predictability. - Subhadeep Aich; Rajanikant Sakariya; Vivek Joshi (ISQED, 2025)

Die Area Reduction by Decongesting Top Channels Using Novel Feedthrough Insertion Methodology in Hierarchical SoC Designs. - Rajanikant Sakariya; Subhadeep Aich; Vivek Joshi; Roger Griesmer (ISQED, 2025)