An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel. - Davy Choi; Richard Pierson; Fredrick Trafton; Benjamin Sheahan; Venugopal Gopinathan; Glenn Mayfield; Indumini Ranmuthu; Srinivasan Venkatraman; Vivek Pawar; Owen Lee; William Giolma; William Krenik; et al. (IEEE J. Solid State Circuits, 1994)

A 2.5 V 10 bit SAR ADC. - Subhashish Mukherjee; C. Srinivasan; Vivek Pawar; Sumeet Mathur; Kiran Godbole; Eric Soenen (VLSI Design, 1997)

Automated Machine Learning Algorithm for Kidney, Kidney Tumor, Kidney Cyst Segmentation in Computed Tomography Scans. - Vivek Pawar; Bharadwaj Kss (KiTS@MICCAI, 2021)