Vivek S. Nandakumar

Affiliations:
  • VLSI-CAD Lab, University of California, Santa Barbara, CA, USA


According to our database1, Vivek S. Nandakumar authored at least 6 papers between 2010 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2014
On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study.
IEEE Comput. Archit. Lett., 2014

System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2012
A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

2011
Low power, high throughput network-on-chip fabric for 3D multicore processors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Layout effects in fine grain 3D integrated regular microprocessor blocks.
Proceedings of the 48th Design Automation Conference, 2011

2010
Statistical static timing analysis flow for transistor level macros in a microprocessor.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010


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