Statistical static timing analysis flow for transistor level macros in a microprocessor. - Vivek S. Nandakumar; David Newmark; Yaping Zhan; Malgorzata Marek-Sadowska (ISQED, 2010)

Layout effects in fine grain 3D integrated regular microprocessor blocks. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (DAC, 2011)

Low power, high throughput network-on-chip fabric for 3D multicore processors. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (ICCD, 2011)

A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (DAC, 2014)

On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study. - Vivek S. Nandakumar; Malgorzata Marek-Sadowska (IEEE Comput. Archit. Lett., 2014)