A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs. - Viveka Konandur Rajanna; Bharadwaj Amrutur (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications. - Viveka Konandur Rajanna; Massimo Alioto (CICC, 2019)

SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. - Viveka Konandur Rajanna; Sachin Taneja; Massimo Alioto (ESSDERC, 2021)

36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. - Sachin Taneja; Viveka Konandur Rajanna; Massimo Alioto (ISSCC, 2021)

Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density. - Prachi Agarwal; Viveka Konandur Rajanna; Toh Wei Da; Benjamin C. K. Tee; Massimo Alioto (VLSI Circuits, 2021)

On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications. - Viveka Konandur Rajanna; Massimo Alioto (IEEE J. Solid State Circuits, 2021)

DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm. - Animesh Gupta; Viveka Konandur Rajanna; Thoithoi Salam; Saurabh Jain; Orazio Aiello; Paolo Crovetti; Massimo Alioto (CICC, 2022)

Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks. - Viveka Konandur Rajanna; Himadri Singh Raghav; Tianqi Wang 004; Massimo Alioto (VLSI Technology and Circuits, 2022)

In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. - Sachin Taneja; Viveka Konandur Rajanna; Massimo Alioto (IEEE J. Solid State Circuits, 2022)

Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems. - Karim Ali Ahmed; Ruiyuan Yang; Praveenakumar Shivappa Salamani; Viveka Konandur Rajanna; Massimo Alioto (ESSCIRC, 2023)

Energy-Efficient Computation in Constrained Systems with Machine Learning Workloads. - Viveka Konandur Rajanna (iSES, 2023)

ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. - Joydeep Basu; Sachin Taneja; Viveka Konandur Rajanna; Tianqi Wang 004; Massimo Alioto (VLSI Technology and Circuits, 2023)

Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. - Animesh Gupta; Sayan Kumar; Viveka Konandur Rajanna; Sachin Taneja; Massimo Alioto (VLSI Technology and Circuits, 2023)

SRAM Physically Unclonable Function Extracting Static Entropy from Every Bitcell Transistor for 6 bit/bitcell and Data Fingerprinting Capability for Provenance Assurance. - Tianqi Wang 004; Joydeep Basu; Viveka Konandur Rajanna; Massimo Alioto (A-SSCC, 2024)

122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm. - Animesh Gupta; Japesh Vohra; Viveka Konandur Rajanna; Massimo Alioto (VLSI Technology and Circuits, 2024)