A novel methodology for hierarchical test generation using functional constraint composition. - Vivekananda M. Vedula; Jacob A. Abraham (HLDVT, 2000)

FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. - Vivekananda M. Vedula; Jacob A. Abraham (DATE, 2002)

Native Mode Functional Self-Test Generation for Systems-on-Chip. - Kamalnayan Jayaraman; Vivekananda M. Vedula; Jacob A. Abraham (ISQED, 2002)

Verifying Properties Using Sequential ATPG. - Jacob A. Abraham; Vivekananda M. Vedula; Daniel G. Saab (ITC, 2002)

Program Slicing for Hierarchical Test Generation. - Vivekananda M. Vedula; Jacob A. Abraham; Jayanta Bhadra (VTS, 2002)

Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. - Daniel G. Saab; Jacob A. Abraham; Vivekananda M. Vedula (VLSI Design, 2003)

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. - Vivekananda M. Vedula; Jacob A. Abraham; Jayanta Bhadra; Raghuram S. Tupuri (J. Electron. Test., 2003)

Program Slicing for ATPG-Based Property Checking. - Vivekananda M. Vedula; Whitney J. Townsend; Jacob A. Abraham (VLSI Design, 2004)

A Scalable Symbolic Simulator for Verilog RTL. - Sasidhar Sunkari; Supratik Chakraborty; Vivekananda M. Vedula; Kailasnath Maneparambil (MTV, 2007)

Controllability-driven Power Virus Generation for Digital Circuits. - K. Najeeb; Karthik Gururaj; V. Kamakoti 001; Vivekananda M. Vedula (VLSI Design, 2007)

Power Virus Generation Using Behavioral Models of Circuits. - K. Najeeb; Vishnu Vardhan Reddy Konda; Siva Kumar Sastry Hari; V. Kamakoti 001; Vivekananda M. Vedula (VTS, 2007)

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. - K. Najeeb; Karthik Gururaj; V. Kamakoti 001; Vivekananda M. Vedula (J. Low Power Electron., 2007)

Automatic Constraint Based Test Generation for Behavioral HDL Models. - Siva Kumar Sastry Hari; Vishnu Vardhan Reddy Konda; V. Kamakoti 001; Vivekananda M. Vedula; K. S. Maneperambil (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A Unified Formal Framework for Analyzing Functional and Speed-path Properties. - Oswaldo Olivo; Sandip Ray; Jayanta Bhadra; Vivekananda M. Vedula (MTV, 2011)