Verifying SystemC using an intermediate verification language and symbolic simulation. - Hoang Minh Le 001; Daniel Große; Vladimir Herdt; Rolf Drechsler (DAC, 2013)

Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. - Vladimir Herdt; Hoang Minh Le 001; Daniel Große; Rolf Drechsler (ATVA, 2015)

Verifying SystemC using stateful symbolic simulation. - Vladimir Herdt; Hoang Minh Le 001; Rolf Drechsler (DAC, 2015)

Complete Symbolic Simulation of SystemC Models - Efficient Formal Verification of Finite Non-Terminating Programs - Vladimir Herdt (Springer, 2016)

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. - Vladimir Herdt; Hoang Minh Le 001; Daniel Große; Rolf Drechsler (CAV (2), 2016)

Towards formal verification of real-world SystemC TLM peripheral models - a case study. - Hoang Minh Le 001; Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2016)

On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (FDL, 2016)

Compiled symbolic simulation for systemC. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (ICCAD, 2016)

Data flow testing for virtual prototypes. - Muhammad Hassan 002; Vladimir Herdt; Hoang M. Le; Mingsong Chen 001; Daniel Große; Rolf Drechsler (DATE, 2017)

Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (FDL (Selected Papers), 2017)

Early SoC security validation by VP-based static information flow analysis. - Muhammad Hassan 002; Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (ICCAD, 2017)

Towards fully automated TLM-to-RTL property refinement. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (DATE, 2018)

Resilience evaluation via symbolic fault injection on intermediate code. - Hoang M. Le; Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2018)

Extensible and Configurable RISC-V Based Virtual Prototype. - Vladimir Herdt; Daniel Große; Hoang M. Le; Rolf Drechsler (FDL, 2018)

Towards Automated Refinement of TLM Properties to RTL. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (MBMV, 2018)

Maximizing power state cross coverage in firmware-based power management. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (ASP-DAC, 2019)

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. - Vladimir Herdt; Daniel Große; Hoang M. Le; Rolf Drechsler (DAC, 2019)

Verifying Instruction Set Simulators using Coverage-guided Fuzzing*. - Vladimir Herdt; Daniel Große; Hoang M. Le; Rolf Drechsler (DATE, 2019)

Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. - Tim Meywerk; Marcel Walter; Vladimir Herdt; Daniel Große; Rolf Drechsler (DSD, 2019)

Systematic RISC-V based Firmware Design⋆. - Vladimir Herdt; Daniel Große; Rolf Drechsler; Christoph Gerum; Alexander Jung; Joscha Benz; Oliver Bringmann 001; Michael Schwarz 010; Dominik Stoffel; Wolfgang Kunz (FDL, 2019)

Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (Int. J. Softw. Tools Technol. Transf., 2019)

Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Efficient modeling, verification and analysis techniques to enhance the virtual prototype based design flow for embedded systems. - Vladimir Herdt (2019)

RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. - Vladimir Herdt; Daniel Große; Rolf Drechsler (ATVA, 2020)

Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*. - Vladimir Herdt; Daniel Große; Rolf Drechsler (DAC, 2020)

Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. - Pascal Pieper; Vladimir Herdt; Daniel Große; Rolf Drechsler (DAC, 2020)

Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*. - Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2020)

Towards Specification and Testing of RISC-V ISA Compliance⋆. - Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2020)

Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. - Vladimir Herdt; Daniel Große; Eyck Jentzsch; Rolf Drechsler (FDL, 2020)

Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. - Vladimir Herdt; Daniel Große; Jonas Wloka; Tim Güneysu; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2020)

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. - Vladimir Herdt; Daniel Große; Sören Tempel; Rolf Drechsler (ICCD, 2020)

Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. - Tim Meywerk; Marcel Walter; Vladimir Herdt; Jan Kleinekathöfer; Daniel Große; Rolf Drechsler (ISoLA (3), 2020)

Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow. - Vladimir Herdt; Rolf Drechsler (ISVLSI, 2020)

RISC-V based virtual prototype: An extensible and configurable platform for the system-level. - Vladimir Herdt; Daniel Große; Pascal Pieper; Rolf Drechsler (J. Syst. Archit., 2020)

Verbessertes Virtual Prototyping für den Entwurfsablauf. - Vladimir Herdt (Ausgezeichnete Informatikdissertationen, 2020)

Mutation-based Compliance Testing for RISC-V. - Vladimir Herdt; Sören Tempel; Daniel Große; Rolf Drechsler (ASP-DAC, 2021)

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (DAC, 2021)

Vertical IP Protection of the Next-Generation Devices: Quo Vadis? - Shubham Rai; Siddharth Garg; Christian Pilato; Vladimir Herdt; Elmira Moussavi; Dominik Sisejkovic; Ramesh Karri; Rolf Drechsler; Farhad Merchant; Akash Kumar 001 (DATE, 2021)

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (DATE, 2021)

RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. - Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (FDL, 2021)

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (FDL, 2021)

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. - Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (MBMV, 2021)

Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. - Frank Riese; Vladimir Herdt; Daniel Große; Rolf Drechsler (VLSI-SoC, 2021)

Toward RISC-V CSR Compliance Testing. - Niklas Bruns; Vladimir Herdt; Daniel Große; Rolf Drechsler (IEEE Embed. Syst. Lett., 2021)

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. - Vladimir Herdt; Daniel Große; Sören Tempel; Rolf Drechsler (J. Syst. Archit., 2021)

Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (Zenodo, 2021)

Automated Detection of Spatial Memory Safety Violations for Constrained Devices. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (ASP-DAC, 2022)

SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (ATVA, 2022)

Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. - Pascal Pieper; Vladimir Herdt; Daniel Große; Rolf Drechsler (DAC, 2022)

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. - Niklas Bruns; Vladimir Herdt; Eyck Jentzsch; Rolf Drechsler (DATE, 2022)

The Scale4Edge RISC-V Ecosystem. - Wolfgang Ecker; Peer Adelt; Wolfgang Müller 003; Reinhold Heckmann; Milos Krstic; Vladimir Herdt; Rolf Drechsler; Gerhard Angst; Ralf Wimmer 001; Andreas Mauderer; Rafael Stahl; Karsten Emrich; et al. (DATE, 2022)

Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. - Milan Funck; Vladimir Herdt; Rolf Drechsler (DDECS, 2022)

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. - Sallar Ahmadi-Pour; Sangeet Saha; Vladimir Herdt; Rolf Drechsler; Klaus D. McDonald-Maier (DSD, 2022)

Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. - Niklas Bruns; Vladimir Herdt; Rolf Drechsler (FDL, 2022)

Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. - Alexander Fratzer; Vladimir Herdt; Christoph Lüth; Rolf Drechsler (FDL, 2022)

3D Visualization of Symbolic Execution Traces. - Jan Zielasko; Sören Tempel; Vladimir Herdt; Rolf Drechsler (FDL, 2022)

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. - Niklas Bruns; Vladimir Herdt; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2022)

Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. - Pascal Pieper; Vladimir Herdt; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2022)

Simulation-Based Debugging of Formal Environment Models. - Tim Meywerk; Arthur Niedzwiecki; Vladimir Herdt; Rolf Drechsler (MED, 2022)

Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. - Vladimir Herdt; Rolf Drechsler (Sci. China Inf. Sci., 2022)

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (IEEE Embed. Syst. Lett., 2022)

The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. - Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (J. Syst. Archit., 2022)

SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (J. Syst. Archit., 2022)

Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (Zenodo, 2022)

Processor Verification using Symbolic Execution: A RISC-V Case-Study. - Niklas Bruns; Vladimir Herdt; Rolf Drechsler (DATE, 2023)

Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. - Milan Funck; Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler (FDL, 2023)

Coverage-Guided Fuzzing for Plan-Based Robotics. - Tim Meywerk; Vladimir Herdt; Rolf Drechsler (ICAART (2), 2023)

Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (Zenodo, 2023)

Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. - Sören Tempel; Vladimir Herdt; Rolf Drechsler (IEEE Internet Things J., 2023)