On-chip inductance modeling and analysis. - Kaushik Gala; Vladimir Zolotov; Rajendran Panda; Brian Young; Junfeng Wang; David T. Blaauw (DAC, 2000)

ClariNet: a noise analysis tool for deep submicron design. - Rafi Levy; David T. Blaauw; Gabi Braca; Aurobindo Dasgupta; Amir Grinshpon; Chanhee Oh; Boaz Orshav; Supamas Sirichotiyakul; Vladimir Zolotov (DAC, 2000)

On-chip inductance modeling. - David T. Blaauw; Kaushik Gala; Vladimir Zolotov; Rajendran Panda; Junfeng Wang (ACM Great Lakes Symposium on VLSI, 2000)

Slope Propagation in Static Timing Analysis. - David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Chanhee Oh; Rajendran Panda (ICCAD, 2000)

Model and analysis for combined package and on-chip power grid simulation. - Rajendran Panda; David T. Blaauw; Rajat Chaudhry; Vladimir Zolotov; Brian Young; Ravi Ramaraju (ISLPED, 2000)

Inductance 101: Analysis and Design Issues. - Kaushik Gala; David T. Blaauw; Junfeng Wang; Vladimir Zolotov; Min Zhao 001 (DAC, 2001)

Driver Modeling and Alignment for Worst-Case Delay Noise. - Supamas Sirichotiyakul; David T. Blaauw; Chanhee Oh; Rafi Levy; Vladimir Zolotov; Jingyan Zuo (DAC, 2001)

False-Noise Analysis using Logic Implications. - Alexey Glebov; Sergey Gavrilov; David T. Blaauw; Supamas Sirichotiyakul; Chanhee Oh; Vladimir Zolotov (ICCAD, 2001)

A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. - Murat R. Becer; David T. Blaauw; Supamas Sirichotiyakul; Chanhee Oh; Vladimir Zolotov; Jingyan Zuo; Rafi Levy; Ibrahim N. Hajj (ISQED, 2001)

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . - Murat R. Becer; Vladimir Zolotov; David T. Blaauw; Rajendran Panda; Ibrahim N. Hajj (DATE, 2002)

A precorrected-FFT method for simulating on-chip inductance. - Haitian Hu; David T. Blaauw; Vladimir Zolotov; Kaushik Gala; Min Zhao 001; Rajendran Panda; Sachin S. Sapatnekar (ICCAD, 2002)

Noise propagation and failure criteria for VLSI designs. - Vladimir Zolotov; David T. Blaauw; Supamas Sirichotiyakul; Murat R. Becer; Chanhee Oh; Rajendran Panda; Amir Grinshpon; Rafi Levy (ICCAD, 2002)

False-Noise Analysis Using Resolution Method. - Alexey Glebov; Sergey Gavrilov; David T. Blaauw; Vladimir Zolotov; Rajendran Panda; Chanhee Oh (ISQED, 2002)

Noise Injection and Propagation in High Performance Designs. - Vladimir Zolotov; David T. Blaauw; Rajendran Panda; Chanhee Oh (ISQED, 2002)

Statistical timing analysis using bounds and selective enumeration. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Sarma B. K. Vrudhula (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Worst case clock skew under power supply variations. - Min Zhao 001; Kaushik Gala; Vladimir Zolotov; Yuhong Fu; Rajendran Panda; R. Ramkumar; Bhuwan K. Agrawal (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Slope propagation in static timing analysis. - David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

False-noise analysis using logic implications. - Alexey Glebov; Sergey Gavrilov; David T. Blaauw; Vladimir Zolotov (ACM Trans. Design Autom. Electr. Syst., 2002)

Inductance model and analysis methodology for high-speed on-chip interconnect. - Kaushik Gala; David T. Blaauw; Vladimir Zolotov; Pravin M. Vaidya; Anil Joshi (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Statistical delay computation considering spatial correlations. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Min Zhao 001; Kaushik Gala; Rajendran Panda (ASP-DAC, 2003)

Computation and Refinement of Statistical Bounds on Circuit Delay. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Sarma B. K. Vrudhula (DAC, 2003)

Post-route gate sizing for crosstalk noise reduction. - Murat R. Becer; David T. Blaauw; Ilan Algor; Rajendran Panda; Chanhee Oh; Vladimir Zolotov; Ibrahim N. Hajj (DAC, 2003)

Statistical Timing Analysis Using Bounds. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Sarma B. K. Vrudhula (DATE, 2003)

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov (ICCAD, 2003)

Statistical Clock Skew Analysis Considering Intra-Die Process Variations. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov (ICCAD, 2003)

SOI Transistor Model for Fast Transient Simulation. - D. Nadezhin; Sergey Gavrilov; Alexey Glebov; Y. Egorov; Vladimir Zolotov; David T. Blaauw; Rajendran Panda; Murat R. Becer; Alexandre Ardelea; A. Patel (ICCAD, 2003)

Vectorless Analysis of Supply Noise Induced Delay Variation. - Sanjay Pant; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda (ICCAD, 2003)

Table look-up based compact modeling for on-chip interconnect timing and noise analysis. - Haitian Hu; David T. Blaauw; Vladimir Zolotov; Kaushik Gala; Min Zhao 001; Rajendran Panda; Sachin S. Sapatnekar (ISCAS (4), 2003)

Static Electromigration Analysis for Signal Interconnects. - Chanhee Oh; David T. Blaauw; Murat R. Becer; Vladimir Zolotov; Rajendran Panda; Aurobindo Dasgupta (ISQED, 2003)

Statistical timing analysis using bounds and selective enumeration. - Aseem Agarwal; Vladimir Zolotov; David T. Blaauw (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Static electromigration analysis for on-chip signal interconnects. - David T. Blaauw; Chanhee Oh; Vladimir Zolotov; Aurobindo Dasgupta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Fast on-chip inductance simulation using a precorrected-FFT method. - Haitian Hu; David T. Blaauw; Vladimir Zolotov; Kaushik Gala; Min Zhao 001; Rajendran Panda; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Static timing analysis using backward signal propagation. - Dongwoo Lee; Vladimir Zolotov; David T. Blaauw (DAC, 2004)

A stochastic approach To power grid analysis. - Sanjay Pant; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda (DAC, 2004)

False-Noise Analysis for Domino Circuits. - Alexey Glebov; Sergey Gavrilov; Vladimir Zolotov; Chanhee Oh; Rajendran Panda; Murat R. Becer (DATE, 2004)

Delay noise pessimism reduction by logic correlations. - Alexey Glebov; Sergey Gavrilov; R. Soloviev; Vladimir Zolotov; Murat R. Becer; Chanhee Oh; Rajendran Panda (ICCAD, 2004)

A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. - Chanhee Oh; Haldun Haznedar; Martin Gall; Amir Grinshpon; Vladimir Zolotov; Pon Sung Ku; Rajendran Panda (ISQED, 2004)

Statistical clock skew analysis considering intradie-process variations. - Aseem Agarwal; Vladimir Zolotov; David T. Blaauw (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Postroute gate sizing for crosstalk noise reduction. - Murat R. Becer; David T. Blaauw; Ilan Algor; Rajendran Panda; Chanhee Oh; Vladimir Zolotov; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Circuit optimization using statistical static timing analysis. - Aseem Agarwal; Kaviraj Chopra; David T. Blaauw; Vladimir Zolotov (DAC, 2005)

Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. - Hongliang Chang; Vladimir Zolotov; Sambasivan Narayan; Chandu Visweswariah (DAC, 2005)

Optimization objectives and models of variation for statistical gate sizing. - Matthew R. Guthaus; Natesan Venkateswaran; Vladimir Zolotov; Dennis Sylvester; Richard B. Brown (ACM Great Lakes Symposium on VLSI, 2005)

Pessimism reduction in crosstalk noise aware STA. - Murat R. Becer; Vladimir Zolotov; Rajendran Panda; Amir Grinshpon; Ilan Algor; Rafi Levy; Chanhee Oh (ICCAD, 2005)

Gate sizing using incremental parameterized statistical timing analysis. - Matthew R. Guthaus; Natesan Venkateswaran; Chandu Visweswariah; Vladimir Zolotov (ICCAD, 2005)

Accurate delay computation for noisy waveform shapes. - Amit Jain; David T. Blaauw; Vladimir Zolotov (ICCAD, 2005)

Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. - Saumil Shah; Ashish Srivastava; Dushyant Sharma; Dennis Sylvester; David T. Blaauw; Vladimir Zolotov (ICCAD, 2005)

Criticality computation in parameterized statistical timing. - Jinjun Xiong; Vladimir Zolotov; Natesan Venkateswaran; Chandu Visweswariah (DAC, 2006)

Impact of stress-induced backflow on full-chip electromigration risk assessment. - Haldun Haznedar; Martin Gall; Vladimir Zolotov; Pon Sung Ku; Chanhee Oh; Rajendran Panda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Optimal placement of power-supply pads and pins. - Min Zhao 001; Yuhong Fu; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Variation-aware performance verification using at-speed structural test and statistical timing. - Vikram Iyengar; Jinjun Xiong; Subbayyan Venkatesan; Vladimir Zolotov; David E. Lackey; Peter A. Habitz; Chandu Visweswariah (ICCAD, 2007)

Compact modeling of variational waveforms. - Vladimir Zolotov; Jinjun Xiong; Soroush Abbaspour; David J. Hathaway; Chandu Visweswariah (ICCAD, 2007)

Robust Extraction of Spatial Correlation. - Jinjun Xiong; Vladimir Zolotov; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Static timing: Back to our roots. - Ruiming Chen; Lizheng Zhang; Vladimir Zolotov; Chandu Visweswariah; Jinjun Xiong (ASP-DAC, 2008)

Incremental Criticality and Yield Gradients. - Jinjun Xiong; Vladimir Zolotov; Chandu Visweswariah (DATE, 2008)

Optimal Margin Computation for At-Speed Test. - Jinjun Xiong; Vladimir Zolotov; Chandu Visweswariah; Peter A. Habitz (DATE, 2008)

Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. - Howard Chen 001; Scott Neely; Jinjun Xiong; Vladimir Zolotov; Chandu Visweswariah (PATMOS, 2008)

Coupling Noise. - Rajendran Panda; Vladimir Zolotov; Murat R. Becer (Handbook of Algorithms for Physical Design Automation, 2008)

Statistical multilayer process space coverage for at-speed test. - Jinjun Xiong; Yiyu Shi 001; Vladimir Zolotov; Chandu Visweswariah (DAC, 2009)

Statistical ordering of correlated timing quantities and its application for path ranking. - Jinjun Xiong; Chandu Visweswariah; Vladimir Zolotov (DAC, 2009)

Pre-ATPG path selection for near optimal post-ATPG process space coverage. - Jiniun Xionq; Yiyu Shi 001; Vladimir Zolotov; Chandu Visweswariah (ICCAD, 2009)

Voltage binning under process variation. - Vladimir Zolotov; Chandu Visweswariah; Jinjun Xiong (ICCAD, 2009)

Statistical Power Analysis for High-Performance Processors. - Howard Chen 001; Scott Neely; Jinjun Xiong; Vladimir Zolotov; Chandu Visweswariah (J. Low Power Electron., 2009)

Optimal Test Margin Computation for At-Speed Structural Test. - Jinjun Xiong; Vladimir Zolotov; Chandu Visweswariah; Peter A. Habitz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Transistor sizing of custom high-performance digital circuits with parametric yield considerations. - Daniel K. Beece; Jinjun Xiong; Chandu Visweswariah; Vladimir Zolotov; Yifang Liu (DAC, 2010)

Statistical Path Selection for At-Speed Test. - Vladimir Zolotov; Jinjun Xiong; Hanif Fatemi; Chandu Visweswariah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Path criticality computation in parameterized statistical timing analysis. - Jaeyong Chung; Jinjun Xiong; Vladimir Zolotov; Jacob A. Abraham (ASP-DAC, 2011)

Optimal statistical chip disposition. - Vladimir Zolotov; Jinjun Xiong (ICCAD, 2011)

Reversible statistical max/min operation: concept and applications to timing. - Debjit Sinha; Chandu Visweswariah; Natesan Venkateswaran; Jinjun Xiong; Vladimir Zolotov (DAC, 2012)

Timing analysis with nonseparable statistical and deterministic variations. - Vladimir Zolotov; Debjit Sinha; Jeffrey G. Hemmett; Eric A. Foreman; Chandu Visweswariah; Jinjun Xiong; Jeremy Leitzen; Natesan Venkateswaran (DAC, 2012)

Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. - Jaeyong Chung; Jinjun Xiong; Vladimir Zolotov; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Testability-Driven Statistical Path Selection. - Jaeyong Chung; Jinjun Xiong; Vladimir Zolotov; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Order statistics for correlated random variables and its application to at-speed testing. - Yiyu Shi 001; Jinjun Xiong; Vladimir Zolotov; Chandu Visweswariah (ACM Trans. Design Autom. Electr. Syst., 2013)

Variation aware cross-talk aggressor alignment by mixed integer linear programming. - Vladimir Zolotov; Peter Feldmann (DAC, 2015)

Practical statistical static timing analysis with current source models. - Debjit Sinha; Vladimir Zolotov; Sheshashayee K. Raghunathan; Michael H. Wood; Kerim Kalafala (DAC, 2016)

Generation and use of statistical timing macro-models considering slew and load variability. - Debjit Sinha; Vladimir Zolotov; Jin Hu; Sheshashayee K. Raghunathan; Adil Bhanji; Christine M. Casey (ICCAD, 2016)

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. - Debjit Sinha; Vladimir Zolotov; Eric Fluhr; Michael H. Wood; Jeffrey Ritzinger; Natesan Venkateswaran; Stephen Shuma (VLSID, 2016)

Analysis and Optimization of fastText Linear Text Classifier. - Vladimir Zolotov; David Kung (CoRR, 2017)

Large Data Flow Graphs in Limited GPU Memory. - Geert Janssen; Vladimir Zolotov; Tung D. Le (IEEE BigData, 2019)

CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. - Ruchir Puri; David S. Kung 001; Geert Janssen; Wei Zhang 022; Giacomo Domeniconi; Vladimir Zolotov; Julian Dolby; Jie Chen 007; Mihir R. Choudhury; Lindsey Decker; Veronika Thost; Luca Buratti; et al. (NeurIPS Datasets and Benchmarks, 2021)

Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. - Ruchir Puri; David S. Kung 001; Geert Janssen; Wei Zhang 022; Giacomo Domeniconi; Vladimir Zolotov; Julian Dolby; Jie Chen 007; Mihir R. Choudhury; Lindsey Decker; Veronika Thost; Luca Buratti; et al. (CoRR, 2021)