Design of optimum interpolation filters for digital demodulators. - Vojin Zivojnovic; Heinrich Meyr (ISCAS, 1993)

High-Level Software Synthesis for the Design of Communication Systems. - Sebastian Ritz; Matthias Pankert; Vojin Zivojnovic; Heinrich Meyr (IEEE J. Sel. Areas Commun., 1993)

Retiming of DSP programs for optimum vectorization. - Vojin Zivojnovic; Sebastian Ritz; Heinrich Meyr (ICASSP (2), 1994)

Compiled HW/SW Co-Simulation. - Vojin Zivojnovic; Heinrich Meyr (DAC, 1996)

Hierarchization of a priori defined dataflow subgraphs. - Markus Willems; Vojin Zivojnovic; Sebastian Ritz (ICASSP, 1996)

On retiming of multirate DSP algorithms. - Vojin Zivojnovic; Rainer Schoenen (ICASSP, 1996)

DSP Processor/Compiler Co-Design: A Quantitative Approach. - Vojin Zivojnovic; Stefan Pees; C. Schälger; Markus Willems; Rainer Schoenen; Heinrich Meyr (ISSS, 1996)

On core and more: a design perspective for systems-on-a-chip. - Stefan Pees; Martin Vaupel; Vojin Zivojnovic; Heinrich Meyr (ASAP, 1997)

An upper bound of the throughput of multirate multiprocessor schedules. - Rainer Schoenen; Vojin Zivojnovic; Heinrich Meyr (ICASSP, 1997)

Modulo-addressing utilization in automatic software synthesis for digital signal processors. - Markus Willems; Holger Keding; Vojin Zivojnovic; Heinrich Meyr (ICASSP, 1997)

Minimum Fisher information spectral analysis. - Vojin Zivojnovic; Dominikus Noll (ICASSP, 1997)

Compiled Simulation of Programmable DSP Architectures. - Vojin Zivojnovic; Steven W. K. Tjiang; Heinrich Meyr (J. VLSI Signal Process., 1997)

Minimum Fisher information of moment-constrained distributions with application to robust blind identification. - Vojin Zivojnovic (Signal Process., 1998)

Der quantitative Ansatz zum gleichzeitigen Entwurf der DSP Architektur und des Compilers. - Vojin Zivojnovic (Shaker, 1998)

Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification. - Lisa M. Guerra; Joachim Fitzner; Dipankar Talukdar; Chris Schläger; Bassam Tabbara; Vojin Zivojnovic (DAC, 1999)

LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. - Stefan Pees; Andreas Hoffmann 002; Vojin Zivojnovic; Heinrich Meyr (DAC, 1999)

Formal model for system-level power management design. - Mirela Simonovic; Vojin Zivojnovic; Lazar Saranovac (DATE, 2017)