Acceleration of transistor-level evolution using Xilinx Zynq Platform. - Vojtech Mrazek; Zdenek Vasícek (ICES, 2014)

Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. - Vojtech Mrazek; Zdenek Vasícek (EUC, 2015)

Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. - Vojtech Mrazek; Zdenek Vasícek (EuroGP, 2015)

Evolutionary Approximation of Software for Embedded Systems: Median Function. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (GECCO (Companion), 2015)

Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. - Radek Hrbacek; Vojtech Mrazek; Zdenek Vasícek (DTIS, 2016)

Design of power-efficient approximate multipliers for approximate artificial neural networks. - Vojtech Mrazek; Syed Shakib Sarwar; Lukás Sekanina; Zdenek Vasícek; Kaushik Roy 001 (ICCAD, 2016)

Automatic design of arbitrary-size approximate sorting networks with error guarantee. - Vojtech Mrazek; Zdenek Vasícek (PATMOS, 2016)

Evolutionary design of polymorphic gates using ambipolar transistors. - Jan Nevoral; Richard Ruzicka; Vojtech Mrazek (SSCI, 2016)

Evolutionary functional approximation of circuits implemented into FPGAs. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (SSCI, 2016)

EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. - Vojtech Mrazek; Radek Hrbacek; Zdenek Vasícek; Lukás Sekanina (DATE, 2017)

Towards low power approximate DCT architecture for HEVC standard. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2017)

Parallel optimization of transistor level circuits using cartesian genetic programming. - Vojtech Mrazek; Zdenek Vasícek (GECCO (Companion), 2017)

Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (ICCAD, 2017)

Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. - Muhammad Shafique 001; Rehan Hafiz; Muhammad Usama Javed; Sarmad Abbas; Lukás Sekanina; Zdenek Vasícek; Vojtech Mrazek (ISVLSI, 2017)

Trading between quality and non-functional properties of median filter in embedded systems. - Zdenek Vasícek; Vojtech Mrazek (Genet. Program. Evolvable Mach., 2017)

Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (AHS, 2018)

ADAC: Automated Design of Approximate Circuits. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (CAV (1), 2018)

Evolving boolean functions for fast and efficient randomness testing. - Vojtech Mrazek; Marek Sýs; Zdenek Vasícek; Lukás Sekanina; Vashek Matyas (GECCO, 2018)

Evolutionary design of large approximate adders optimized for various error criteria. - Vojtech Mrazek; Zdenek Vasícek (GECCO (Companion), 2018)

Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. - Lukás Sekanina; Vojtech Mrazek; Zdenek Vasícek (ICECS, 2018)

Role of circuit representation in evolutionary design of energy-efficient approximate circuits. - Vojtech Mrazek; Zdenek Vasícek; Radek Hrbacek (IET Comput. Digit. Tech., 2018)

Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Honglan Jiang; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Automated Search-Based Functional Approximation for Digital Circuits. - Lukás Sekanina; Zdenek Vasícek; Vojtech Mrazek (Approximate Circuits, 2019)

autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. - Vojtech Mrazek; Muhammad Abdullah Hanif; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (DAC, 2019)

Automated Circuit Approximation Method Driven by Data Distribution. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2019)

ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Abdullah Hanif; Muhammad Shafique 001 (ICCAD, 2019)

Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. - Vojtech Mrazek; Lukás Sekanina; Roland Dobai; Marek Sýs; Petr Svenda (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. - Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek (AICAS, 2020)

A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. - Alessio Colucci; Alberto Marchisio; Beatrice Bussolino; Vojtech Mrazek; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (CODES+ISSS, 2020)

ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (DAC, 2020)

ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. - Alberto Marchisio; Vojtech Mrazek; Muhammad Abdullah Hanif; Muhammad Shafique 001 (DATE, 2020)

TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. - Filip Vaverka; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (DATE, 2020)

NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. - Alberto Marchisio; Andrea Massa; Vojtech Mrazek; Beatrice Bussolino; Maurizio Martina; Muhammad Shafique 001 (ICCAD, 2020)

Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Tomás Vojnar (SAT, 2020)

Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (Appl. Soft Comput., 2020)

Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. - Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. - Mohammad Saeed Ansari; Vojtech Mrazek; Bruce F. Cockburn; Lukás Sekanina; Zdenek Vasícek; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Evolutionary Neural Architecture Search Supporting Approximate Multipliers. - Michal Pinos; Vojtech Mrazek; Lukás Sekanina (EuroGP, 2021)

Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. - David Hodan; Vojtech Mrazek; Zdenek Vasícek (Genet. Program. Evolvable Mach., 2021)

DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. - Alberto Marchisio; Vojtech Mrazek; Muhammad Abdullah Hanif; Muhammad Shafique 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. - Alberto Marchisio; Vojtech Mrazek; Muhammad Abdullah Hanif; Muhammad Shafique 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. - Jan Klhufek; Vojtech Mrazek (DDECS, 2022)

Designing Approximate Arithmetic Circuits with Combined Error Constraints. - Milan Ceska 001; Jirí Matyás; Vojtech Mrazek; Tomás Vojnar (DSD, 2022)

Optimization of BDD-based Approximation Error Metrics Calculations. - Vojtech Mrazek (ISVLSI, 2022)

Evolutionary Design of Reduced Precision Preprocessor for Levodopa-Induced Dyskinesia Classifier. - Martin Hurta; Michaela Drahosova; Vojtech Mrazek (PPSN (1), 2022)

RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. - Alberto Marchisio; Vojtech Mrazek; Andrea Massa; Beatrice Bussolino; Maurizio Martina; Muhammad Shafique 001 (IEEE Access, 2022)

Designing Approximate Arithmetic Circuits with Combined Error Constraints. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Tomás Vojnar (CoRR, 2022)

Evolutionary approximation and neural architecture search. - Michal Pinos; Vojtech Mrazek; Lukás Sekanina (Genet. Program. Evolvable Mach., 2022)

SagTree: Towards efficient mutation in evolutionary circuit approximation. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (Swarm Evol. Comput., 2022)

ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. - Martin Hurta; Vojtech Mrazek; Michaela Drahosova; Lukás Sekanina (DATE, 2023)

MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. - Martin Hurta; Vojtech Mrazek; Michaela Drahosova; Lukás Sekanina (DDECS, 2023)

Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). - Vojtech Mrazek (DDECS, 2023)

Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. - Michal Pinos; Vojtech Mrazek; Lukás Sekanina (DDECS, 2023)

Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. - Vojtech Mrazek; Soyiba Jawed; Muhammad Arif 008; Aamir Saeed Malik (GECCO, 2023)

Energy Complexity Model for Convolutional Neural Networks. - Jirí Síma; Petra Vidnerová; Vojtech Mrazek (ICANN (10), 2023)

Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (ICCAD, 2023)

autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (CoRR, 2023)

Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. - Michal Pinos; Vojtech Mrazek; Filip Vaverka; Zdenek Vasícek; Lukás Sekanina (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2024)

Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. - Jan Klhufek; Miroslav Safar; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (DDECS, 2024)

Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. - Vojtech Mrazek; Argyris Kokkinis; Panagiotis Papanikolaou; Zdenek Vasícek; Kostas Siozios; Georgios Tzimpragos; Mehdi B. Tahoori; Georgios Zervakis 001 (ICCAD, 2024)

ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. - Michal Pinos; Lukás Sekanina; Vojtech Mrazek (IJCNN, 2024)

Energy Complexity of Convolutional Neural Networks. - Jirí Síma; Petra Vidnerová; Vojtech Mrazek (Neural Comput., 2024)

Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. - Filip Masar; Vojtech Mrazek; Lukás Sekanina (DATE, 2025)

Inference Energy Analysis in Context of Hardware-Aware NAS. - Michal Pinos; Jan Klhufek; Vojtech Mrazek; Lukás Sekanina (DDECS, 2025)

Multi-objective Evolutionary Design of Explainable EEG Classifier. - Martin Hurta; Anna Ovesna; Vojtech Mrazek; Lukás Sekanina (EuroGP, 2025)

AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. - Vojtech Mrazek; Zdenek Vasícek (ISCAS, 2025)

ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate Computing. - Ondrej Vlcek; Vojtech Mrazek (CoRR, 2025)