Low swing dual threshold voltage domino logic. - Volkan Kursun; Eby G. Friedman (ACM Great Lakes Symposium on VLSI, 2002)

Managing static leakage energy in microprocessor functional units. - Steve Dropsho; Volkan Kursun; David H. Albonesi; Sandhya Dwarkadas; Eby G. Friedman (MICRO, 2002)

Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. - Volkan Kursun; Siva G. Narendra; Vivek De; Eby G. Friedman (ISQED, 2003)

Dynamically Tuning Processor Resources with Adaptive Processing. - David H. Albonesi; Rajeev Balasubramonian; Steve Dropsho; Sandhya Dwarkadas; Eby G. Friedman; Michael C. Huang 001; Volkan Kursun; Grigorios Magklis; Michael L. Scott; Greg Semeraro; Pradip Bose; Alper Buyuktosunoglu; et al. (Computer, 2003)

Domino logic with variable threshold voltage keeper. - Volkan Kursun; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. - Volkan Kursun; Siva G. Narendra; Vivek De; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. - Volkan Kursun; Eby G. Friedman (ISCAS (2), 2004)

Forward body biased keeper for enhanced noise immunity in domino logic circuits. - Volkan Kursun; Eby G. Friedman (ISCAS (2), 2004)

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. - Gerhard Schrom; Peter Hazucha; Jae-Hong Hahn; Volkan Kursun; Donald S. Gardner; Siva G. Narendra; Tanay Karnik; Vivek De (ISLPED, 2004)

Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. - Volkan Kursun; Eby G. Friedman (ISQED, 2004)

High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. - Volkan Kursun; Siva G. Narendra; Vivek De; Eby G. Friedman (ISQED, 2004)

Low-voltage-swing monolithic dc-dc conversion. - Volkan Kursun; Siva G. Narendra; Vivek K. De; Eby G. Friedman (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. - Volkan Kursun; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Cascode buffer for monolithic voltage conversion operating at high input supply voltages. - Volkan Kursun; Gerhard Schrom; Vivek De; Eby G. Friedman; Siva G. Narendra (ISCAS (1), 2005)

Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling. - Zhiyu Liu; Volkan Kursun (SoCC, 2005)

Monolithic voltage conversion in low-voltage CMOS technologies. - Volkan Kursun; Vivek De; Eby G. Friedman; Siva G. Narendra (Microelectron. J., 2005)

A design methodology for temperature variation insensitive low power circuits. - Ranjith Kumar; Volkan Kursun (ACM Great Lakes Symposium on VLSI, 2006)

Leakage current starved domino logic. - Zhiyu Liu; Volkan Kursun (ACM Great Lakes Symposium on VLSI, 2006)

Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies. - Ranjith Kumar; Volkan Kursun (ISCAS, 2006)

Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies. - Volkan Kursun; Zhiyu Liu (ISCAS, 2006)

Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. - Zhiyu Liu; Volkan Kursun (ISQED, 2006)

Leakage Biased Sleep Switch Domino Logic. - Zhiyu Liu; Volkan Kursun (ISQED, 2006)

High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages. - Zhiyu Liu; Volkan Kursun (ISVLSI, 2006)

Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison. - Ranjith Kumar; Volkan Kursun (SoCC, 2006)

High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling. - Zhiyu Liu; Volkan Kursun (SoCC, 2006)

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current. - Zhiyu Liu; Volkan Kursun (Microelectron. J., 2006)

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits. - Ranjith Kumar; Volkan Kursun (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies. - Zhiyu Liu; Volkan Kursun (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Leakage Biased pMOS Sleep Switch Dynamic Circuits. - Zhiyu Liu; Volkan Kursun (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits. - Ranjith Kumar; Volkan Kursun (ICECS, 2007)

New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability. - Zhiyu Liu; Volkan Kursun (ICECS, 2007)

Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density. - Sherif A. Tawfik; Volkan Kursun (ICECS, 2007)

Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption. - Sherif A. Tawfik; Volkan Kursun (ICECS, 2007)

Leakage-Aware Design of Nanometer SoC. - Volkan Kursun; Sherif A. Tawfik; Zhiyu Liu (ISCAS, 2007)

Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions. - Zhiyu Liu; Volkan Kursun (ISCAS, 2007)

High Read Stability and Low Leakage Cache Memory Cell. - Zhiyu Liu; Volkan Kursun (ISCAS, 2007)

Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. - Sherif A. Tawfik; Volkan Kursun (ISCAS, 2007)

Multi-Vth Level Conversion Circuits for Multi-VDD Systems. - Sherif A. Tawfik; Volkan Kursun (ISCAS, 2007)

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. - Sherif A. Tawfik; Volkan Kursun (ISLPED, 2007)

Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. - Zhiyu Liu; Volkan Kursun (ISQED, 2007)

Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. - Sherif A. Tawfik; Volkan Kursun (ISQED, 2007)

An independent-gate FinFET SRAM cell for high data stability and enhanced integration density. - Zhiyu Liu; Sherif A. Tawfik; Volkan Kursun (SoCC, 2007)

Low-power high-performance FinFET sequential circuits. - Sherif A. Tawfik; Volkan Kursun (SoCC, 2007)

Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits. - Ranjith Kumar; Volkan Kursun (Microelectron. J., 2007)

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. - Zhiyu Liu; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption. - Sherif A. Tawfik; Volkan Kursun (APCCAS, 2008)

Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic. - Sherif A. Tawfik; Volkan Kursun (APCCAS, 2008)

Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. - Sherif A. Tawfik; Volkan Kursun (ISCAS, 2008)

Low power and robust 7T dual-Vt SRAM circuit. - Sherif A. Tawfik; Volkan Kursun (ISCAS, 2008)

Dynamic wordline voltage swing for low leakage and stable static memory banks. - Sherif A. Tawfik; Volkan Kursun (ISCAS, 2008)

Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. - Zhiyu Liu; Sherif A. Tawfik; Volkan Kursun (ISQED, 2008)

Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. - Sherif A. Tawfik; Volkan Kursun (ISQED, 2008)

Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. - Sherif A. Tawfik; Volkan Kursun (ISQED, 2008)

Temperature-Adaptive Energy Reduction Techniques for Nano-CMOS Circuits Displaying Reversed temperature Dependence. - Ranjith Kumar; Volkan Kursun (J. Circuits Syst. Comput., 2008)

Technique for Accurate Power and Energy Measurement with the Computer-Aided Design Tools. - Ranjith Kumar; Zhiyu Liu; Volkan Kursun (J. Circuits Syst. Comput., 2008)

Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption. - Sherif A. Tawfik; Volkan Kursun (J. Circuits Syst. Comput., 2008)

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits. - Ranjith Kumar; Volkan Kursun (Microelectron. J., 2008)

Characterization of a Novel Nine-Transistor SRAM Cell. - Zhiyu Liu; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power. - Sherif A. Tawfik; Volkan Kursun (J. Low Power Electron., 2009)

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays. - Ranjith Kumar; Volkan Kursun (Microelectron. J., 2009)

FinFET domino logic with independent gate keepers. - Sherif A. Tawfik; Volkan Kursun (Microelectron. J., 2009)

Low Power and High Speed Multi Threshold Voltage Interface Circuits. - Sherif A. Tawfik; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops. - Hailong Jiao; Volkan Kursun (ISCAS, 2010)

Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits. - Hailong Jiao; Volkan Kursun (VLSI-SoC, 2010)

Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits. - Hailong Jiao; Volkan Kursun (VLSI-SoC (Selected Papers), 2010)

Low-Leakage and Compact Registers with Easy-Sleep Mode. - Hailong Jiao; Volkan Kursun (J. Low Power Electron., 2010)

Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew. - Sherif A. Tawfik; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Leakage current and bottom gate voltage considerations in developing maximum performance 16nm N-channel carbon nanotube transistors. - Yanan Sun 003; Volkan Kursun (ISCAS, 2011)

Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical quality. - Hong Zhu 009; Volkan Kursun (ISOCC, 2011)

Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits. - Hailong Jiao; Volkan Kursun (SoCC, 2011)

Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs. - Yanan Sun 003; Volkan Kursun (VLSI-SoC, 2011)

Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias. - Hailong Jiao; Volkan Kursun (J. Circuits Syst. Comput., 2011)

Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Multi-Threshold Voltage FinFET Sequential Circuits. - Sherif A. Tawfik; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations. - Hailong Jiao; Volkan Kursun (ISCAS, 2012)

Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits. - Hailong Jiao; Volkan Kursun (ISOCC, 2012)

NP dynamic CMOS resurrection with carbon nanotube field effect transistors. - Yanan Sun 003; Volkan Kursun (ISOCC, 2012)

Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption. - Shairfe Muhammad Salahuddin; Volkan Kursun (ICECS, 2013)

Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability. - Shairfe Muhammad Salahuddin; Hailong Jiao; Volkan Kursun (ISCAS, 2013)

Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors. - Yanan Sun 003; Volkan Kursun (ISCAS, 2013)

Novel dual-threshold-voltage energy-efficient buffers for driving large extrinsic load capacitance. - Hong Zhu 009; Volkan Kursun (ISCAS, 2013)

A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. - Shairfe Muhammad Salahuddin; Hailong Jiao; Volkan Kursun (ISQED, 2013)

Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells. - Hong Zhu 009; Volkan Kursun (ISQED, 2013)

Ground gated 8T SRAM cells with enhanced read and hold data stability. - Hailong Jiao; Volkan Kursun (ISVLSI, 2013)

Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins. - Khawar Sarfraz; Volkan Kursun (ISVLSI, 2013)

Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits. - Hailong Jiao; Volkan Kursun (VLSI-SoC, 2013)

Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins. - Yanan Sun 003; Hailong Jiao; Volkan Kursun (ICM, 2014)

Triple-threshold-voltage 9-transistor SRAM cell for data stability and energy-efficiency at ultra-low power supply voltages. - Hong Zhu 009; Volkan Kursun (ICM, 2014)

A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells. - Hong Zhu 009; Volkan Kursun (ISCAS, 2014)

High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins. - Shairfe Muhammad Salahuddin; Volkan Kursun (ISIC, 2014)

Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits. - Hailong Jiao; Volkan Kursun (Microelectron. J., 2014)

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits. - Yanan Sun 003; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations. - Hong Zhu 009; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs. - Hong Zhu 009; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed. - Yanan Sun 003; Volkan Kursun (ISCAS, 2015)

2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents. - Hong Zhu 009; Volkan Kursun (ISCAS, 2015)

A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors. - Yanan Sun 003; Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode. - Hailong Jiao; Yongmin Qiu; Volkan Kursun (IOLTS, 2016)

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode. - Hailong Jiao; Yongmin Qiu; Volkan Kursun (Integr., 2016)

Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability. - Shairfe Muhammad Salahuddin; Volkan Kursun (J. Circuits Syst. Comput., 2016)

Low power and robust memory circuits with asymmetrical ground gating. - Hailong Jiao; Yongmin Qiu; Volkan Kursun (Microelectron. J., 2016)

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ASICON, 2017)

Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. - Yanan Sun 003; Weifeng He; Zhigang Mao; Volkan Kursun (Microelectron. J., 2017)

Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. - Jiachen Jiang; Yanan Sun 003; Weifeng He; Zhigang Mao; Volkan Kursun (ASICON, 2019)

Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ICEIC, 2019)

Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers. - Anil Kumar Gundu; Volkan Kursun (PATMOS, 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters. - Anil Kumar Gundu; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology. - Anil Kumar Gundu; Volkan Kursun (SoCC, 2021)

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater. - Anil Kumar Gundu; Volkan Kursun (Integr., 2021)

Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology. - Anil Kumar Gundu; Volkan Kursun (ISCAS, 2022)