Accurate simulation of phase noise in RF MEMS VCOs. - Manas Behera; Volodymyr Kratyuk; Yutao Hu 001; Kartikeya Mayaram (ISCAS (3), 2004)

A low spur fractional-N frequency synthesizer architecture. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (ISCAS (3), 2005)

Analysis of supply and ground noise sensitivity in ring and LC oscillators. - Volodymyr Kratyuk; Igor Vytyaz; Un-Ku Moon; Kartikeya Mayaram (ISCAS (6), 2005)

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (CICC, 2007)

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter. - Pavan Kumar Hanumolu; Volodymyr Kratyuk; Gu-Yeon Wei; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

A Digital PLL With a Stochastic Time-to-Digital Converter. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Kerem Ok; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)