Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. - Vu Manh Tuan; Yohei Hasegawa; Naohiro Katsura; Hideharu Amano (ARC, 2006)

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. - Yohei Hasegawa; Shohei Abe; Shunsuke Kurotaki; Vu Manh Tuan; Naohiro Katsura; Takuro Nakamura; Takashi Nishimura; Hideharu Amano (IPDPS, 2006)

A cost-effective context memory structure for dynamically reconfigurable processors. - Masayasu Suzuki; Yohei Hasegawa; Vu Manh Tuan; Shohei Abe; Hideharu Amano (IPDPS, 2006)

Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. - Vu Manh Tuan; Yohei Hasegawa; Hideharu Amano (ERSA, 2007)

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. - Vu Manh Tuan; Hideharu Amano (ARC, 2008)

A Method for Capturing State Data on Dynamically Reconfigurable Processors. - Vu Manh Tuan; Hideharu Amano (ERSA, 2008)

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. - Vu Manh Tuan; Hideharu Amano (IEICE Trans. Inf. Syst., 2008)

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors. - Vu Manh Tuan; Hideharu Amano (IEICE Trans. Inf. Syst., 2008)

Evaluation of a multicore reconfigurable architecture with variable core sizes. - Vu Manh Tuan; Naohiro Katsura; Hiroki Matsutani; Hideharu Amano (IPDPS, 2009)