Generator of randomized pseudorandom numbers. - Jan Havel; A. N. Morozevich; Vyacheslav N. Yarmolik (Kybernetika, 1983)

Signature Testability of PLA. - E. P. Kalosha; Vyacheslav N. Yarmolik; Mark G. Karpovsky (FPL, 1994)

Transparent Memory Testing for Pattern-Sensitive Faults. - Mark G. Karpovsky; Vyacheslav N. Yarmolik (ITC, 1994)

Aliasing-free Signature Analysis for RAM BIST. - Vyacheslav N. Yarmolik; Michael Nicolaidis; O. Kebichi (ITC, 1994)

Zero aliasing ROM BIST. - O. Kebichi; Vyacheslav N. Yarmolik; Michael Nicolaidis (J. Electron. Test., 1994)

Pseudo-exhaustive word-oriented DRAM testing. - Mark G. Karpovsky; Ad J. van de Goor; V. N. Yarmolik (ED&TC, 1995)

Exact Aliasing Computation for RAM BIST. - O. Kebichi; Michael Nicolaidis; Vyacheslav N. Yarmolik (ITC, 1995)

RAM Testing Algorithm for Detection Linked Coupling Faults. - V. G. Mikitjuk; V. N. Yarmolik; Ad J. van de Goor (ED&TC, 1996)

March LR: a test for realistic linked faults. - Ad J. van de Goor; Georgi Gaydadjiev; V. G. Mikitjuk; Vyacheslav N. Yarmolik (VTS, 1996)

Transparent random access memory testing for pattern sensitive faults. - Mark G. Karpovsky; Vyacheslav N. Yarmolik (J. Electron. Test., 1996)

March LA: a test for linked memory faults. - Ad J. van de Goor; Georgi Gaydadjiev; Vyacheslav N. Yarmolik; V. G. Mikitjuk (ED&TC, 1997)

March PS(23N) Test for DRAM Pattern-Sensitive Faults. - Vyacheslav N. Yarmolik; Yuri V. Klimets; Serge N. Demidenko (Asian Test Symposium, 1998)

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. - Vyacheslav N. Yarmolik; Sybille Hellebrand; Hans-Joachim Wunderlich (DATE, 1998)

BIST Module for Mixed-Signal Circuits. - Serge N. Demidenko; Vincenzo Piuri; Vyacheslav N. Yarmolik; A. Shmidman (DFT, 1998)

Symmetric Transparent BIST for RAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Vyacheslav N. Yarmolik (DATE, 1999)

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. - Vyacheslav N. Yarmolik; I. V. Bykov; Sybille Hellebrand; Hans-Joachim Wunderlich (EDCC, 1999)

Error Detecting Refreshment for Embedded DRAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets; Vyacheslav N. Yarmolik (VTS, 1999)

Efficient Online and Offline Testing of Embedded DRAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets; Vyacheslav N. Yarmolik (IEEE Trans. Computers, 2002)

Two-pattern test generation with low power consumption based on LFSR. - Miroslaw Puczko; V. N. Yarmolik (Information Processing and Security Systems, 2005)

Cryptography and Steganography: teaching experience. - Bartosz Sokol; V. N. Yarmolik (Enhanced Methods in Computer Security, Biometric and Artificial Intelligence Systems, 2005)

Designing cryptographic key generators with low power consumption. - Miroslaw Puczko; V. N. Yarmolik (DELTA, 2006)

Obfuscation as Intellectual Rights Protection in VHDL Language. - Maciej Brzozowski; Vyacheslav N. Yarmolik (CISIM, 2007)

Multiple Errors Detection Technique for RAM. - Sergei B. Musin; Alexander A. Ivaniuk; Vyacheslav N. Yarmolik (DDECS, 2007)

Injection of functional faults in VHDL-description of digital devices. - A. A. Ivanyuk; V. N. Yarmolik (Autom. Control. Comput. Sci., 2007)

Multi Background Memory Testing. - Ireneusz Mrozek; Vyacheslav N. Yarmolik; Eugenia Buslowska (CISIM, 2008)

Optimal Backgrounds Selection for Multi Run Memory Testing. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (DDECS, 2008)

A new approach to the design of built-in internal memory self-testing devices. - A. A. Ivanyuk; V. N. Yarmolik (Autom. Control. Comput. Sci., 2008)

Determination of the optimal initial states for multiple-run RAM testing. - S. V. Yarmolik; Alexander N. Kurbatski; V. N. Yarmolik (Autom. Control. Comput. Sci., 2008)

Nondestructive RAM testing based on multiple signature comparison. - S. V. Yarmolik; V. N. Yarmolik (Autom. Control. Comput. Sci., 2009)

Generalized adaptive signature analysis. - S. V. Yarmolik; Vyacheslav N. Yarmolik (Autom. Control. Comput. Sci., 2010)

The synthesis of probability tests with a small number of kits. - S. V. Yarmolik; V. N. Yarmolik (Autom. Control. Comput. Sci., 2011)

Iterative Antirandom Testing. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (J. Electron. Test., 2012)

Antirandom Test Vectors for BIST in Hardware/Software Systems. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (Fundam. Informaticae, 2012)

Generating modified Sobol sequences for multiple run march memory tests. - V. N. Yarmolik; S. V. Yarmolik (Autom. Control. Comput. Sci., 2013)

Address sequences. - Vyacheslav N. Yarmolik; Svetlana V. Yarmolik (Autom. Control. Comput. Sci., 2014)

Controlled method of random test synthesis. - Vyacheslav N. Yarmolik; Ireneusz Mrozek; Svetlana V. Yarmolik (Autom. Control. Comput. Sci., 2015)

Methods of Synthesis of Controlled Random Tests. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (CISIM, 2016)

Multiple Controlled Random Testing. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (Fundam. Informaticae, 2016)

Optimal Controlled Random Tests. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (CISIM, 2017)

Two-Run RAM March Testing with Address Decimation. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (J. Circuits Syst. Comput., 2017)

Multi-Run March Tests for Pattern Sensitive Faults in RAM. - Eugenia Buslowska; Vyacheslav N. Yarmolik (EWDTS, 2018)

Pseudo-Exhaustive Random Access Memory Testing Based on March Tests with Random Background Variation. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (EWDTS, 2018)

Transparent Memory Tests Based on the Double Address Sequences. - Ireneusz Mrozek; Vyacheslav N. Yarmolik (Entropy, 2021)

Synthesis of Test Sequences with a Given Switching Activity. - V. N. Yarmolik; Nikolai A. Shevchenko (Autom. Remote. Control., 2022)

Universal Address Sequence Generator for Memory Built-in Self-test. - Ireneusz Mrozek; Nikolai A. Shevchenko; Vyacheslav N. Yarmolik (Fundam. Informaticae, 2022)