Regular logic fabrics for a via patterned gate array (VPGA). - Kim Yaw Tong; V. Kheterpal; Vyacheslav Rovner; Lawrence T. Pileggi; Herman Schmit (CICC, 2003)

Exploring regular fabrics to optimize the performance-cost trade-off. - Lawrence T. Pileggi; Herman Schmit; Andrzej J. Strojwas; Padmini Gopalakrishnan; V. Kheterpal; Aneesh Koorapaty; Chetan Patel; Vyacheslav Rovner; Kim Yaw Tong (DAC, 2003)

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. - Thomas J. Vogels; Thomas Zanon; Rao Desineni; R. D. (Shawn) Blanton; Wojciech Maly; Jason G. Brown; Jeffrey E. Nelson; Y. Fei; X. Huang; Padmini Gopalakrishnan; Mahim Mishra; Vyacheslav Rovner; et al. (ITC, 2004)

Design methodology for IC manufacturability based on regular logic-bricks. - V. Kheterpal; Vyacheslav Rovner; T. G. Hersan; D. Motiani; Y. Takegawa; Andrzej J. Strojwas; Lawrence T. Pileggi (DAC, 2005)

Creating an affordable 22nm node using design-lithography co-optimization. - Andrzej J. Strojwas; Tejas Jhaveri; Vyacheslav Rovner; Lawrence T. Pileggi (DAC, 2009)

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. - Tejas Jhaveri; Vyacheslav Rovner; Lars Liebmann; Larry T. Pileggi; Andrzej J. Strojwas; Jason Hibbeler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)