Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation. - Vyas Krishnan; Srinivas Katkoori (ISQED, 2006)

A genetic algorithm for the design space exploration of datapaths during high-level synthesis. - Vyas Krishnan; Srinivas Katkoori (IEEE Trans. Evol. Comput., 2006)

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. - Vyas Krishnan; Srinivas Katkoori (ISQED, 2007)

Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. - Vyas Krishnan; Srinivas Katkoori (VLSI-SoC, 2007)

Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis. - Vyas Krishnan; Srinivas Katkoori (VLSI Design, 2008)

Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis. - Vyas Krishnan; Srinivas Katkoori (VLSI Design, 2009)

TABS: Temperature-Aware Layout-Driven Behavioral Synthesis. - Vyas Krishnan; Srinivas Katkoori (IEEE Trans. Very Large Scale Integr. Syst., 2010)