Power Balanced Gates Insensitive to Routing Capacitance Mismatch. - Konrad J. Kulikowski; Vyas Venkataraman; Zhen Wang 001; Alexander Taubin (DATE, 2008)

Asynchronous balanced gates tolerant to interconnect variability. - Konrad J. Kulikowski; Vyas Venkataraman; Zhen Wang 001; Alexander Taubin; Mark G. Karpovsky (ISCAS, 2008)

Accelerating multi-party scheduling for transaction-level modeling. - Di Wang; Vyas Venkataraman; Zhen Wang 001; Wei Qin; Hangsheng Wang; Mrinal Bose; Jayanta Bhadra (ACM Great Lakes Symposium on VLSI, 2009)

Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. - Vyas Venkataraman; Di Wang; Atabak Mahram; Wei Qin; Mrinal Bose; Jayanta Bhadra (ISVLSI, 2009)

Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. - Vyas Venkataraman; Di Wang; Wei Qin; Mrinal Bose; Jayanta Bhadra (MTV, 2009)