A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic. - W. A. J. Waller; S. M. Aziz (VLSI, 1993)

On Testability of Differential Split-Level CMOS Circuits. - S. M. Aziz; W. A. J. Waller (VLSI Design, 1994)

Rapid layout synthesis for analog VLSI. - Les T. Walczowski; W. A. J. Waller; D. Nalbantis; Keng-Hua Shi (ICECS, 1996)

Analogue layout generation by World Wide Web server-based agents. - Les T. Walczowski; D. Nalbantis; W. A. J. Waller; Keng-Hua Shi (ED&TC, 1997)

Multiple server WWW-based synthesis of VLSI circuits. - D. Nalbantis; Les T. Walczowski; W. A. J. Waller (ICECS, 1998)

A digital engineering curriculum with integrated, Windows-based EDA tools. - Les T. Walczowski; Keith R. Dimond; W. A. J. Waller (ICECS, 1998)

Java servlet technology for analogue module generation. - Les T. Walczowski; W. A. J. Waller (ICECS, 1999)