FPGA technology mapping optimization by rewiring algorithms. - Wai-Chung Tang; Wing-Hang Lo; Yu-Liang Wu; Shih-Chieh Chang (ISCAS (6), 2005)

How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs. - Catherine L. Zhou; Wai-Chung Tang; Wing-Hang Lo; Yu-Liang Wu (DAC, 2007)

Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. - Wai-Chung Tang; Wing-Hang Lo; Yu-Liang Wu (ISCAS, 2007)

A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. - Wai-Chung Tang; Catherine L. Zhou; Yu-Liang Wu (ERSA, 2008)

Improving FPGA designs with incremental logic resynthesis and shortcut-based routing architecture. - Wai-Chung Tang (2008)

Logic synthesis for low power using clock gating and rewiring. - Tak-Kei Lam; Steve Yang; Wai-Chung Tang; Yu-Liang Wu (ACM Great Lakes Symposium on VLSI, 2010)

On applying erroneous clock gating conditions to further cut down power. - Tak-Kei Lam; Xiaoqing Yang; Wai-Chung Tang; Yu-Liang Wu (ASP-DAC, 2011)

Grid-to-ports clock routing for high performance microprocessor designs. - Haitong Tian; Wai-Chung Tang; Evangeline F. Y. Young; Cliff C. N. Sze (ISPD, 2011)

ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. - Xing Wei; Wai-Chung Tang; Yi Diao; Yu-Liang Wu (ASP-DAC, 2012)

Almost every wire is removable: A modeling and solution for removing any circuit wire. - Xiaoqing Yang; Tak-Kei Lam; Wai-Chung Tang; Yu-Liang Wu (DATE, 2012)

WRIP: logic restructuring techniques for wirelength-driven incremental placement. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ACM Great Lakes Symposium on VLSI, 2012)

Postgrid Clock Routing for High Performance Microprocessor Designs. - Haitong Tian; Wai-Chung Tang; Evangeline F. Y. Young; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme. - Tak-Kei Lam; Wai-Chung Tang; Xiaoqing Yang; Yu-Liang Wu (ACM Trans. Design Autom. Electr. Syst., 2012)

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ASP-DAC, 2013)

A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). - Ka-Chun Lam; Wai-Chung Tang; Evangeline F. Y. Young (FPGA, 2014)

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. - Xing Wei; Tak-Kei Lam; Xiaoqing Yang; Wai-Chung Tang; Yi Diao; Yu-Liang Wu (VLSID, 2014)