Implementation of the Ficus Replicated File System. - Richard G. Guy; John S. Heidemann; Wai-Kei Mak; Thomas W. Page Jr.; Gerald J. Popek; Dieter Rothmeier (USENIX Summer, 1990)

Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. - Mee Yee Chan; Francis Y. L. Chin; Chris Chu; Wai-Kei Mak (SPDP, 1993)

On Optimal Board-Level Routing for FPGA-Based Logic Emulation. - Wai-Kei Mak; D. F. Wong 001 (DAC, 1995)

Board-level multi-terminal net routing for FPGA-based logic emulation. - Wai-Kei Mak; D. F. Wong 001 (ICCAD, 1995)

Minimum replication min-cut partitioning. - Wai-Kei Mak; D. F. Wong 001 (ICCAD, 1996)

Channel Segmentation Design for Symmentrical FPGAs. - Wai-Kei Mak; D. F. Wong 001 (ICCD, 1997)

Board-level multiterminal net routing for FPGA-based logic emulation. - Wai-Kei Mak; D. F. Wong 001 (ACM Trans. Design Autom. Electr. Syst., 1997)

Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). - Wai-Kei Mak; D. F. Wong 001 (FPGA, 1998)

Performance-driven board-level routing for FPGA-based logic emulation. - Wai-Kei Mak; D. F. Wong 001 (ICCD, 1998)

A fast hypergraph minimum cut algorithm. - Wai-Kei Mak; D. F. Wong 001 (ISCAS (6), 1999)

Monte Carlo bounding techniques for determining solution quality in stochastic programs. - Wai-Kei Mak; David P. Morton; R. Kevin Wood (Oper. Res. Lett., 1999)

A fast hypergraph min-cut algorithm for circuit partitioning. - Wai-Kei Mak; D. F. Wong 001 (Integr., 2000)

Faster and more accurate wiring evaluation in interconnect-centric floorplanning. - Hung-Ming Chen; D. F. Wong 001; Wai-Kei Mak; Hannah Honghua Yang (ACM Great Lakes Symposium on VLSI, 2001)

Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. - Wai-Kei Mak (ISPD, 2001)

Temporal logic replication for dynamically reconfigurable FPGA partitioning. - Wai-Kei Mak; Evangeline F. Y. Young (ISPD, 2002)

Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. - Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Efficient LUT-based FPGA technology mapping for power minimization. - Hao Li; Wai-Kei Mak; Srinivas Katkoori (ASP-DAC, 2003)

I/O placement for FPGAs with multiple I/O standards. - Wai-Kei Mak (FPGA, 2003)

Clustering based acyclic multi-way partitioning. - Eric S. H. Wong; Evangeline F. Y. Young; Wai-Kei Mak (ACM Great Lakes Symposium on VLSI, 2003)

Force-Directed Performance-Driven Placement Algorithm for FPGAs. - Hao Li; Wai-Kei Mak; Srinivas Katkoori (ISVLSI, 2004)

Power minimization algorithms for LUT-based FPGA technology mapping. - Hao Li; Srinivas Katkoori; Wai-Kei Mak (ACM Trans. Design Autom. Electr. Syst., 2004)

Modern FPGA constrained placement. - Wai-Kei Mak (ASP-DAC, 2005)

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. - Chien-Chang Chen; Wai-Kei Mak (ASP-DAC, 2006)

Voltage Island Generation under Performance Requirement for SoC Designs. - Wai-Kei Mak; Jr-Wei Chen (ASP-DAC, 2007)

Optimal Buffering of FPGA Interconnect for Expected Delay Optimization. - Yi-Ru He; Wai-Kei Mak (FPT, 2007)

Low-power gated and buffered clock network construction. - Wei-Chung Chao; Wai-Kei Mak (ACM Trans. Design Autom. Electr. Syst., 2008)

Guest Editorial: Field Programmable Technology. - George A. Constantinides; Wai-Kei Mak; Theerayod Wiangtong (J. Signal Process. Syst., 2008)

Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. - Cheng-Yu Wang; Wai-Kei Mak (ASP-DAC, 2009)

How to consider shorts and guarantee yield rate improvement for redundant wire insertion. - Fong-Yuan Chang; Ren-Song Tsay; Wai-Kei Mak (ICCAD, 2009)

Pad assignment for die-stacking System-in-Package design. - Yu-Chen Lin; Wai-Kei Mak; Chris Chu; Ting-Chi Wang (ICCAD, 2009)

Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. - Chun-Yu Chuang; Wai-Kei Mak (ISQED, 2009)

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. - De-Yu Liu; Wai-Kei Mak; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2010)

FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. - Gaurav Ajwani; Chris Chu; Wai-Kei Mak (ISPD, 2010)

SafeChoice: a novel clustering algorithm for wirelength-driven placement. - Jackey Z. Yan; Chris Chu; Wai-Kei Mak (ISPD, 2010)

Cut-demand based routing resource allocation and consolidation for routability enhancement. - Fong-Yuan Chang; Sheng-Hsiung Chen; Ren-Song Tsay; Wai-Kei Mak (ASP-DAC, 2011)

Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign. - Seong-I Lei; Wai-Kei Mak (FPL, 2011)

Power-driven flip-flop merging and relocation. - Shao-Huan Wang; Yu-Yi Liang; Tien-Yu Kuo; Wai-Kei Mak (ISPD, 2011)

SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. - Jackey Z. Yan; Chris C. N. Chu; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules. - Yu-Yi Liang; Tien-Yu Kuo; Shao-Huan Wang; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

ISPD11: Power-Driven Flip-Flop Merging and Relocation. - Shao-Huan Wang; Yu-Yi Liang; Tien-Yu Kuo; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Rethinking the Wirelength Benefit of 3-D Integration. - Wai-Kei Mak; Chris Chu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. - Fong-Yuan Chang; Ren-Song Tsay; Wai-Kei Mak; Sheng-Hsiung Chen (ASP-DAC, 2013)

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. - Fong-Yuan Chang; Ren-Song Tsay; Wai-Kei Mak; Sheng-Hsiung Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design. - Seong-I Lei; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. - Cha-Ru Li; Wai-Kei Mak; Ting-Chi Wang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Flexible packed stencil design with multiple shaping apertures for e-beam lithography. - Chris Chu; Wai-Kei Mak (ASP-DAC, 2014)

A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules. - Sheng-Kai Wu; Po-Yi Hsu; Wai-Kei Mak (ASP-DAC, 2014)

Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout. - Yixiao Ding; Chris Chu; Wai-Kei Mak (DAC, 2014)

Double patterning-aware detailed routing with mask usage balancing. - Seong-I Lei; Chris Chu; Wai-Kei Mak (ISQED, 2014)

E-Beam Lithography Character and Stencil Co-Optimization. - Wai-Kei Mak; Chris Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A fast parallel approach for common path pessimism removal. - Chung-Hao Tsai; Wai-Kei Mak (ASP-DAC, 2015)

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. - Yixiao Ding; Chris C. N. Chu; Wai-Kei Mak (DAC, 2015)

Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. - Jyun-Hao Chang; Hsin-I Wu; Hsien-Lun Pai; Ren-Song Tsay; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography. - Chris C. N. Chu; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Minimum implant area-aware placement and threshold voltage refinement. - Seong-I Lei; Wai-Kei Mak; Chris Chu (ASP-DAC, 2016)

Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. - Yixiao Ding; Chris C. N. Chu; Wai-Kei Mak (DAC, 2016)

Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs. - Seong-I Lei; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Optimizing DSA-MP decomposition and redundant via insertion with dummy vias. - Chung-Yao Hung; Peng-Yi Chou; Wai-Kei Mak (ASP-DAC, 2017)

Mixed-Cell-Height Standard Cell Placement Legalization. - Chung-Yao Hung; Peng-Yi Chou; Wai-Kei Mak (ACM Great Lakes Symposium on VLSI, 2017)

Making split fabrication synergistically secure and manufacturable. - Lang Feng 001; Yujie Wang; Jiang Hu 001; Wai-Kei Mak; Jeyavijayan Rajendran (ICCAD, 2017)

Pin Accessibility-Driven Detailed Placement Refinement. - Yixiao Ding; Chris Chu; Wai-Kei Mak (ISPD, 2017)

A routing framework for technology migration with bump encroachment. - Po-Yi Wu; Wai-Kei Mak; Ting-Chi Wang; Cheng Zhuo; Kassan Unda; Yiyu Shi 001 (Integr., 2017)

Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment. - Yixiao Ding; Chris Chu; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement. - Wai-Kei Mak; Wan-Sin Kuo; Shi-Han Zhang; Seong-I Lei; Chris Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

A practical detailed placement algorithm under multi-cell spacing constraints. - Yu-Hsiang Cheng; Ding-Wei Huang; Wai-Kei Mak; Ting-Chi Wang (ICCAD, 2018)

Pin Assignment Optimization for Multi-2.5D FPGA-based Systems. - Wan-Sin Kuo; Shi-Han Zhang; Wai-Kei Mak; Richard Sun; Yoon Kah Leow (ISPD, 2018)

Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement. - Yu-Jin Xie; Kuan-Yu Chen; Wai-Kei Mak (ASP-DAC, 2021)

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits. - Ching-Cheng Wang; Wai-Kei Mak (ICCAD, 2021)

Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs. - Bo-Yang Chen; Chi-Chun Fang; Wai-Kei Mak; Ting-Chi Wang (ISPD, 2021)

Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os. - Yu-Chen Liao; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

HybridGP: Global Placement for Hybrid-Row-Height Designs. - Kuan-Yu Chen; Hsiu-Chu Hsu; Wai-Kei Mak; Ting-Chi Wang (ASP-DAC, 2022)

Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem. - Ching-Yao Huang; Chi-Hsiang Lien; Wai-Kei Mak (ICCAD, 2022)

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. - Meng-Yun Liu; Yu-Cheng Lai; Wai-Kei Mak; Ting-Chi Wang (ICCAD, 2022)

Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement. - Chung-Hsien Wu 001; Wai-Kei Mak; Chris Chu (ISPD, 2022)

Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. - Syuan-Han Liang; Tsu-Ling Hsiung; Wai-Kei Mak; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2023)

Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization. - Yu-Jin Xie; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

CTQr: Control and Timing-Aware Qubit Routing. - Ching-Yao Huang; Wai-Kei Mak (ASPDAC, 2024)

Row Planning and Placement for Hybrid-Row-Height Designs. - Ching-Yao Huang; Wai-Kei Mak (ASPDAC, 2024)

An Effective Netlist Planning Approach for Double-sided Signal Routing. - Tzu-Chuan Lin; Fang-Yu Hsu; Wai-Kei Mak; Ting-Chi Wang (ASPDAC, 2024)

A Bounding Box-based Net Partitioning Method for Double-sided Routing. - Fang-Yu Hsu; Tzu-Chuan Lin; Wai-Kei Mak; Ting-Chi Wang (ACM Great Lakes Symposium on VLSI, 2024)

An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal Routing. - Che-Ping Tsai; Fang-Yu Hsu; Wai-Kei Mak; Ting-Chi Wang (ICCAD, 2024)

Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group Movement. - Bing-Huan Wu; Wai-Kei Mak (ISPD, 2024)

Placement Flow Study and Detailed Placement for Hybrid-Row-Height Designs. - Wei-Kai Fang; Wai-Kei Mak (ACM Trans. Design Autom. Electr. Syst., 2024)

Efficient Qubit Routing Using a Dynamically Extract-and-Route Framework. - Ching-Yao Huang; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)