Aberth's Method for the Parallel Iterative Finding of Polynomial Zeros. - Tien Chi Chen; Wai-Shing Luk (APL, 1994)

The Use of Inexact ODE Solver in Waveform Relaxation Methods on a Massively Parallel Computer. - Wai-Shing Luk; Omar Wing (PP, 1995)

Two New Quorum Based Algorithms for Distributed Mutual Exclusion. - Wai-Shing Luk; Tien-Tsin Wong (ICDCS, 1997)

Waveform Krylov Subspace Methods on a Massively Parallel Computer. - Wai-Shing Luk; Omar Wing (Int. J. High Speed Comput., 1997)

Sampling with Hammersley and Halton Points. - Tien-Tsin Wong; Wai-Shing Luk; Pheng-Ann Heng (J. Graphics, GPU, & Game Tools, 1997)

Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic. - Xuexin Liu; Wai-Shing Luk; Yu Song; Pushan Tang; Xuan Zeng 001 (ASP-DAC, 2007)

WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. - Peng Zhang; Wai-Shing Luk; Yu Song; Jiarong Tong; Pushan Tang; Xuan Zeng 001 (ASP-DAC, 2007)

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. - Yi Wang; Wai-Shing Luk; Xuan Zeng 001; Jun Tao 001; Changhao Yan; Jiarong Tong; Wei Cai 003; Jia Ni (DAC, 2008)

Characterizing Intra-Die Spatial Correlation Using Spectral Density Method. - Qiang Fu; Wai-Shing Luk; Jun Tao 001; Changhao Yan; Xuan Zeng 001 (ISQED, 2008)

Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method. - Qiang Fu; Wai-Shing Luk; Jun Tao 001; Changhao Yan; Xuan Zeng 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips. - Qiang Fu; Wai-Shing Luk; Jun Tao 001; Xuan Zeng 001; Wei Cai 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Fast and lossless graph division method for layout decomposition using SPQR-tree. - Wai-Shing Luk; Huiping Huang (ICCAD, 2010)

An efficient algorithm for multi-domain clock skew scheduling. - Yanling Zhi; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Hengliang Zhu; Xuan Zeng 001 (DATE, 2011)

Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays. - Yanling Zhi; Wai-Shing Luk; Yi Wang; Changhao Yan; Xuan Zeng 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Layout decomposition with pairwise coloring for multiple patterning lithography. - Ye Zhang 011; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Xuan Zeng 001 (ICCAD, 2013)

SmipRef: An efficient method for multi-domain clock skew scheduling. - Yanling Zhi; Wai-Shing Luk; Hai Zhou 001; Xuan Zeng 001 (Integr., 2013)

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. - Yunfeng Yang; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2015)

Multi-parameter clock skew scheduling. - Xingbao Zhou; Wai-Shing Luk; Hai Zhou 001; Fan Yang 001; Changhao Yan; Xuan Zeng 001 (Integr., 2015)

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. - Ye Zhang 011; Wai-Shing Luk; Yunfeng Yang; Hai Zhou 001; Changhao Yan; David Z. Pan; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. - Yunfeng Yang; Wai-Shing Luk; David Z. Pan; Hai Zhou 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Network flow based cut redistribution and insertion for advanced 1D layout design. - Ye Zhang 011; Wai-Shing Luk; Fan Yang 001; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2017)

Layout decomposition for hybrid E-beam and DSA double patterning lithography. - Yunfeng Yang; Fan Yang 001; Wai-Shing Luk; Changhao Yan; Xuan Zeng 001; Xiangdong Hu (ISCAS, 2017)

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. - Yunfeng Yang; Wai-Shing Luk; Hai Zhou 001; David Z. Pan; Dian Zhou; Changhao Yan; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. - Ye Zhang 011; Wenlong Lyu; Wai-Shing Luk; Fan Yang 001; Hai Zhou 001; Dian Zhou; David Z. Pan; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA. - Yunhui Qiu; Jinyu Xie; Hankun Lv; Wenbo Yin; Wai-Shing Luk; Lingli Wang; Bowei Yu; Hua Chen; Xianjun Ge; Zhijian Liao; Xiaozhong Shi (IEEE Trans. Parallel Distributed Syst., 2020)

LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA. - Jingbo Gao; Yu Qian; Yihan Hu 003; Xitian Fan; Wai-Shing Luk; Wei Cao 002; Lingli Wang (FPT, 2021)

MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes. - Shaoyang Sun; Boyin Jin; Jiahang Lou; Jiangnan Li; Yuhang Cao; Jingyuan Li 003; Chen Shen; Yuan Dai; Wenbo Yin; Wai-Shing Luk; Lingli Wang (ASAP, 2024)

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design. - Yiqing Mao; Xuchen Gao; Jiahang Lou; Yunhui Qiu; Wenbo Yin; Wai-Shing Luk; Lingli Wang (FPL, 2024)

Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring. - Yuan Dai; Xuchen Gao; Chen Shen; Bingbing Peng; Wenbo Yin; Wai-Shing Luk; Lingli Wang (ASP-DAC, 2025)

Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution. - Kaixiang Zhu; Wai-Shing Luk; Lingli Wang (ASP-DAC, 2025)

COFFA: A Co-Design Framework for Fused-Grained Reconfigurable Architecture Towards Efficient Irregular Loop Handling. - Yuan Dai; Xuchen Gao; Yunhui Qiu; Jingyuan Li 003; Yuhang Cao; Yiqing Mao; Sichao Chen; Wenbo Yin; Wai-Shing Luk; Lingli Wang (IEEE Trans. Computers, 2025)