Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits. - Waisum Wong; Juin J. Liou; Jiann-Shiun Yuan; David M. Wu (VTS, 1991)

Optimization of on-chip ESD protection structures for minimal parasitic capacitance. - Xiaofang Gao; Juin J. Liou; Joe Bernier; Gregg D. Croft; Waisum Wong; Satya Vishwanathan (Microelectron. Reliab., 2003)

New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology. - Pengpeng Ren; Changze Liu; Sanping Wan; Jiayang Zhang; Zhuoqing Yu; Nie Liu; Yongsheng Sun; Runsheng Wang; Canhui Zhan; Zhenghao Gan; Waisum Wong; Yu Xia; et al. (IRPS, 2018)