A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization. - Waleed El-Halwagy; Mohamed Dessouky; Hassan El-Ghitani (ICECS, 2013)

Analysis and design of analog-based voltage controlled oscillator linearization technique. - Waleed El-Halwagy; Mohamed Dessouky; Hassan El-Ghitani (IDT, 2013)

A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC. - Waleed El-Halwagy; Pedram Mousavi; Masum Hossain (A-SSCC, 2016)

Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter. - Masum Hossain; Amlan Nag; Waleed El-Halwagy; A. K. M. Delwar Hossain; Aurangozeb (A-SSCC, 2016)

Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter. - Masum Hossain; Waleed El-Halwagy; A. K. M. Delwar Hossain; Aurangozeb (IEEE J. Solid State Circuits, 2017)

Investigation of Wideband Substrate-Integrated Vertically-Polarized Electric Dipole Antenna and Arrays for mm-Wave 5G Mobile Devices. - Waleed El-Halwagy; Rashid Mirzavand; Jordan Melzer; Masum Hossain; Pedram Mousavi (IEEE Access, 2018)

A 100-MS/s-5-GS/s, 13-5-bit Nyquist-Rate Reconfigurable Time-Domain ADC. - Waleed El-Halwagy; Pedram Mousavi; Masum Hossain (IEEE Trans. Very Large Scale Integr. Syst., 2018)