Multi-Level Execution In Data-Flow Architectures. - Walid A. Najjar; Jean-Luc Gaudiot (ICPP, 1987)

Reliability and Performance Modelling of Hypercube-Based Mutliprocessors. - Walid A. Najjar; Jean-Luc Gaudiot (Computer Performance and Reliability, 1987)

Parallel Discrete-Event Simulation. - Walid A. Najjar; Jean-Luc Jezouin; Jean-Luc Gaudiot (IEEE Des. Test, 1987)

Network Disconnection in Distributed Systems. - Walid A. Najjar; Jean-Luc Gaudiot (ICDCS, 1988)

A Single-Assignment Language in a Distributed Memory Multiprocessor. - Paraskevas Evripidou; Walid A. Najjar; Jean-Luc Gaudiot (PARLE (2), 1989)

Limits on Scalability in Gracefully Degradable Large-Scale Systems. - Walid A. Najjar; Jean-Luc Gaudiot (SRDS, 1989)

A data-driven execution paradigm for distributed fault-tolerance. - Walid A. Najjar; Jean-Luc Gaudiot (ACM SIGOPS European Workshop, 1990)

Network Resilience: A Measure of Network Fault Tolerance. - Walid A. Najjar; Jean-Luc Gaudiot (IEEE Trans. Computers, 1990)

Network resilience of star graphs: a comparative analysis. - Walid A. Najjar; Pradip K. Srimani (ACM Conference on Computer Science, 1991)

A Quantitative Analysis of Locality in Dataflow Programs. - William Marcus Miller; Walid A. Najjar; A. P. Wim Böhm (MICRO, 1991)

An Analysis of Loop Latency in Dataflow Execution. - Walid A. Najjar; William Marcus Miller; A. P. Wim Böhm (ISCA, 1992)

Generation and Quantitative Evaluation of Dataflow Clusters. - Lucas Roh; Walid A. Najjar; A. P. Wim Böhm (FPCA, 1993)

The Initial Performance of a Bottom-Up Clustering Algorithm for Dataflow Graphs. - Walid A. Najjar; Lucas Roh; A. P. Wim Böhm (Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993)

An evaluation of bottom-up and top-down thread generation techniques. - A. P. Wim Böhm; Walid A. Najjar; Bhanu Shankar; Lucas Roh (MICRO, 1993)

Evaluation of Idealized Adaptive Routing on k-ary n-cubes. - Annette Lagman; Walid A. Najjar; Sumit Sur; Pradip K. Srimani (SPDP, 1993)

A Quantitative Analysis of Dataflow Program Execution - Preliminaries to a Hybrid Design. - Walid A. Najjar; A. P. Wim Böhm; William Marcus Miller (J. Parallel Distributed Comput., 1993)

Conditional Disconnection Probability in Star Graphs. - Walid A. Najjar; Pradip K. Srimani (VLSI Design, 1993)

Exploiting Locality in Hybrid Dataflow Programs. - Walid A. Najjar; A. P. Wim Böhm; William Marcus Miller (Multithreaded Computer Architecture, 1994)

A model for dataflow based vector execution. - William Marcus Miller; Walid A. Najjar; A. P. Wim Böhm (International Conference on Supercomputing, 1994)

An Evaluation of Optimized Threaded Code Generation. - Lucas Roh; Walid A. Najjar; Bhanu Shankar; A. P. Wim Böhm (IFIP PACT, 1994)

Modeling Adaptive Routing in k-ary n-cube Networks. - Walid A. Najjar; Annette Lagman; Sumit Sur; Pradip K. Srimani (MASCOTS, 1994)

An evaluation of medium-grain dataflow code. - Walid A. Najjar; Lucas Roh; A. P. Wim Böhm (Int. J. Parallel Program., 1994)

An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks. - Annette Lagman; Walid A. Najjar; Pradip K. Srimani (IEEE Trans. Computers, 1994)

Authors' Reply. - Walid A. Najjar; Jean-Luc Gaudiot (IEEE Trans. Computers, 1994)

Analysis of communications and overhead reduction in multithreaded execution. - Lucas Roh; Walid A. Najjar (PACT, 1995)

Control of loop parallelism in multithreaded code. - Bhanu Shankar; Lucas Roh; A. P. Wim Böhm; Walid A. Najjar (PACT, 1995)

Design of storage hierarchy in multithreaded architectures. - Lucas Roh; Walid A. Najjar (MICRO, 1995)

Exploiting Data Structure Locality in the Dataflow Model. - William Marcus Miller; Walid A. Najjar; A. P. Wim Böhm (J. Parallel Distributed Comput., 1995)

Analysis of Buffer Design for Adaptive Routing in Direct Networks. - Annette Lagman; Walid A. Najjar (MASCOTS, 1996)

Comparison of two storage models in data-driven multithreaded architectures. - Murali Annavaram; Walid A. Najjar (SPDP, 1996)

Generation, Optimization, and Evaluation of Multithreaded Code. - Lucas Roh; Walid A. Najjar; Bhanu Shankar; A. P. Wim Böhm (J. Parallel Distributed Comput., 1996)

Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers. - Dianne Miller; Walid A. Najjar (IEEE PACT, 1997)

Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router. - Dianne Miller; Walid A. Najjar (PCRCW, 1997)

Foreword to the special issues. - Walid A. Najjar; Gabriel M. Silberman (Int. J. Parallel Program., 1997)

Cameron: High level Language Compilation for Reconfigurable Systems. - Jeffrey Hammes; Robert Rinker; A. P. Wim Böhm; Walid A. Najjar; Bruce A. Draper; J. Ross Beveridge (IEEE PACT, 1999)

Combining Adaptive and Deterministic Routing: Evaluation of a Hybrid Router. - Dianne R. Kumar; Walid A. Najjar (CANPC, 1999)

Advances in the dataflow computational model. - Walid A. Najjar; Edward A. Lee; Guang R. Gao (Parallel Comput., 1999)

Compiling Image Processing Applications to Reconfigurable Hardware. - Robert Rinker; Jeffrey Hammes; Walid A. Najjar; A. P. Wim Böhm; Bruce A. Draper (ASAP, 2000)

Compiling and Optimizing Image Processing Algorithms for FPGAs. - Bruce A. Draper; Walid A. Najjar; A. P. Wim Böhm; Jeffrey Hammes; Robert Rinker; Charlie Ross; Monica Chawathe; José Bins (CAMP, 2000)

A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. - Jeffrey Hammes; Robert Rinker; A. P. Wim Böhm; Walid A. Najjar; Bruce A. Draper (PDPTA, 2000)

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. - Girish Venkataramani; Walid A. Najjar; Fadi J. Kurdahi; Nader Bagherzadeh; A. P. Wim Böhm (CASES, 2001)

The Sisal Project: Real World Functional Programming. - Jean-Luc Gaudiot; Thomas DeBoni; John Feo; A. P. Wim Böhm; Walid A. Najjar; Patrick Miller (Compiler Optimizations for Scalable Parallel Systems Languages, 2001)

One-Step Compilation of Image Processing Applications to FPGAs. - A. P. Wim Böhm; Bruce A. Draper; Walid A. Najjar; Jeffrey Hammes; Robert Rinker; Monica Chawathe; Charlie Ross (FCCM, 2001)

Compiling SA-C Programs to FPGAs: Performance Results. - Bruce A. Draper; A. P. Wim Böhm; Jeffrey Hammes; Walid A. Najjar; J. Ross Beveridge; Charlie Ross; Monica Chawathe; Mitesh Desai; José Bins (ICVS, 2001)

Loop fusion and temporal common subexpression elimination in window-based loops. - Jeffrey Hammes; A. P. Wim Böhm; Charlie Ross; Monica Chawathe; Bruce A. Draper; Robert Rinker; Walid A. Najjar (IPDPS, 2001)

Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes. - Dianne R. Kumar; Walid A. Najjar; Pradip K. Srimani (IPDPS, 2001)

Resource Management in Dataflow-Based Multithreaded Execution. - Lucas Roh; Bhanu Shankar; A. P. Wim Böhm; Walid A. Najjar (J. Parallel Distributed Comput., 2001)

A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes. - Dianne R. Kumar; Walid A. Najjar; Pradip K. Srimani (IEEE Trans. Computers, 2001)

An automated process for compiling dataflow graphs into reconfigurable hardware. - Robert Rinker; M. Carter; A. Patel; Monica Chawathe; Charlie Ross; Jeffrey Hammes; Walid A. Najjar; A. P. Wim Böhm (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Compiling ATR Probing Codes for Execution on FPGA Hardware. - A. P. Wim Böhm; J. Ross Beveridge; Bruce A. Draper; Charlie Ross; Monica Chawathe; Walid A. Najjar (FCCM, 2002)

Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. - Dhananjay Kulkarni; Walid A. Najjar; Robert Rinker; Fadi J. Kurdahi (FCCM, 2002)

Improving Software Performance with Configurable Logic. - Jason R. Villarreal; Dinesh C. Suresh; Greg Stitt; Frank Vahid; Walid A. Najjar (Des. Autom. Embed. Syst., 2002)

Mapping a Single Assignment Programming Language to Reconfigurable Systems. - A. P. Wim Böhm; Jeffrey Hammes; Bruce A. Draper; Monica Chawathe; Charlie Ross; Robert Rinker; Walid A. Najjar (J. Supercomput., 2002)

Power efficient encoding techniques for off-chip data buses. - Dinesh C. Suresh; Banit Agrawal; Jun Yang 002; Walid A. Najjar; Laxmi N. Bhuyan (CASES, 2003)

First results with eBlocks: embedded systems building blocks. - Susan Cotterell; Frank Vahid; Walid A. Najjar; Harry Hsieh (CODES+ISSS, 2003)

FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. - Dinesh C. Suresh; Jun Yang 002; Chuanjun Zhang; Banit Agrawal; Walid A. Najjar (HiPC, 2003)

A Highly-Configurable Cache Architecture for Embedded Systems. - Chuanjun Zhang; Frank Vahid; Walid A. Najjar (ISCA, 2003)

Energy Benefits of a Configurable Line Size Cache for Embedded Systems. - Chuanjun Zhang; Frank Vahid; Walid A. Najjar (ISVLSI, 2003)

Profiling tools for hardware/software partitioning of embedded applications. - Dinesh C. Suresh; Walid A. Najjar; Frank Vahid; Jason R. Villarreal; Greg Stitt (LCTES, 2003)

A Way-Halting Cache for Low-Energy High-Performance Systems. - Chuanjun Zhang; Frank Vahid; Jun Yang 002; Walid A. Najjar (IEEE Comput. Archit. Lett., 2003)

High-Level Language Abstraction for Reconfigurable Computing. - Walid A. Najjar; A. P. Wim Böhm; Bruce A. Draper; Jeffrey Hammes; Robert Rinker; J. Ross Beveridge; Monica Chawathe; Charles Ross (Computer, 2003)

Automatic compilation to a coarse-grained reconfigurable system-opn-chip. - Girish Venkataramani; Walid A. Najjar; Fadi J. Kurdahi; Nader Bagherzadeh; A. P. Wim Böhm; Jeffrey Hammes (ACM Trans. Embed. Comput. Syst., 2003)

From Here to Main-stream: The Present and Future of Reconfigurable Computing. - Walid A. Najjar (ERSA, 2004)

A quantitative analysis of the speedup factors of FPGAs over processors. - Zhi Guo; Walid A. Najjar; Frank Vahid; Kees A. Vissers (FPGA, 2004)

"How Long is Your Belt?" Towards a Single Device for Multiple Functions. - Walid A. Najjar (ICPS, 2004)

Input data reuse in compiling window operations onto reconfigurable hardware. - Zhi Guo; Betul Buyukkurt; Walid A. Najjar (LCTES, 2004)

Optimized Generation of Data-Path from C Codes for FPGAs. - Zhi Guo; Betul Buyukkurt; Walid A. Najjar; Kees A. Vissers (DATE, 2005)

MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices. - Demetrios Zeinalipour-Yazti; Song Lin; Vana Kalogeraki; Dimitrios Gunopulos; Walid A. Najjar (FAST, 2005)

Techniques for synthesizing binaries to an advanced register/memory structure. - Greg Stitt; Zhi Guo; Walid A. Najjar; Frank Vahid (FPGA, 2005)

VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. - Dinesh C. Suresh; Banit Agrawal; Walid A. Najjar; Jun Yang 002 (ICCD, 2005)

Data Acquisition in Sensor Networks with Large Memories. - Demetrios Zeinalipour-Yazti; Vana Kalogeraki; Dimitrios Gunopulos; Walid A. Najjar (ICDE Workshops, 2005)

A tunable bus encoder for off-chip data buses. - Dinesh C. Suresh; Banit Agrawal; Jun Yang 002; Walid A. Najjar (ISLPED, 2005)

Towards In-Situ Data Storage in Sensor Databases. - Demetrios Zeinalipour-Yazti; Vana Kalogeraki; Dimitrios Gunopulos; Anirban Mitra; Anirban Banerjee; Walid A. Najjar (Panhellenic Conference on Informatics, 2005)

Power Efficient Instruction Caches for Embedded Systems. - Dinesh C. Suresh; Walid A. Najjar; Jun Yang 002 (SAMOS, 2005)

RISE - Co-S : high performance sensor storage and Co-processing architecture. - Anirban Banerjee; Abhishek Mitra; Walid A. Najjar; Demetrios Zeinalipour-Yazti; Vana Kalogeraki; Dimitrios Gunopulos (SECON, 2005)

Splitting the sensor node. - Anirban Banerjee; Anirban Mitra; Walid A. Najjar (SenSys, 2005)

A highly configurable cache for low energy embedded systems. - Chuanjun Zhang; Frank Vahid; Walid A. Najjar (ACM Trans. Embed. Comput. Syst., 2005)

Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. - Betul Buyukkurt; Zhi Guo; Walid A. Najjar (ARC, 2006)

Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. - Dinesh C. Suresh; Zhi Guo; Betul Buyukkurt; Walid A. Najjar (ARC, 2006)

Automation of IP Core Interface Generation for Reconfigurable Computing. - Zhi Guo; Abhishek Mitra; Walid A. Najjar (FPL, 2006)

A Compiler Intermediate Representation for Reconfigurable Fabrics. - Zhi Guo; Walid A. Najjar (FPL, 2006)

A code refinement methodology for performance-improved synthesis from C. - Greg Stitt; Frank Vahid; Walid A. Najjar (ICCAD, 2006)

Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. - Abhishek Mitra; Zhi Guo; Anirban Banerjee; Walid A. Najjar (ICCD, 2006)

Compile-time area estimation for LUT-based FPGAs. - Dhananjay Kulkarni; Walid A. Najjar; Robert Rinker; Fadi J. Kurdahi (ACM Trans. Design Autom. Electr. Syst., 2006)

Efficient indexing data structures for flash-based sensor devices. - Song Lin; Demetrios Zeinalipour-Yazti; Vana Kalogeraki; Dimitrios Gunopulos; Walid A. Najjar (ACM Trans. Storage, 2006)

Compiling PCRE to FPGA for accelerating SNORT IDS. - Abhishek Mitra; Walid A. Najjar; Laxmi N. Bhuyan (ANCS, 2007)

Compiling code accelerators for FPGAs. - Walid A. Najjar (CODES+ISSS, 2007)

A one-shot configurable-cache tuner for improved energy and performance. - Ann Gordon-Ross; Pablo Viana; Frank Vahid; Walid A. Najjar; Edna Barros (DATE, 2007)

Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. - Kai Schleupen; Scott Lekuch; Ryan Mannion; Zhi Guo; Walid A. Najjar; Frank Vahid (FPL, 2007)

Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. - Betul Buyukkurt; Walid A. Najjar (FPL, 2008)

Compiled hardware acceleration of Molecular Dynamics code. - Jason R. Villarreal; Walid A. Najjar (FPL, 2008)

A Compiler Intermediate Representation for Reconfigurable Fabrics. - Zhi Guo; Betul Buyukkurt; John Cortes; Abhishek Mitra; Walid A. Najjar (Int. J. Parallel Program., 2008)

OpenFPGA CoreLib core library interoperability effort. - Michael J. Wirthlin; Daniel S. Poznanovic; P. Sundararajan; Alan J. Coppola; D. Pellerin; Walid A. Najjar; R. Bruce; M. Babst; O. Pritchard; Paolo Palazzari; Georgi Kuzmanov (Parallel Comput., 2008)

Efficient hardware code generation for FPGAs. - Zhi Guo; Walid A. Najjar; Betul Buyukkurt (ACM Trans. Archit. Code Optim., 2008)

Boosting XML filtering through a scalable FPGA-based architecture. - Abhishek Mitra; Marcos R. Vieira; Petko Bakalov; Vassilis J. Tsotras; Walid A. Najjar (CIDR, 2009)

Reconfigurable Computing in the New Age of Parallelism. - Walid A. Najjar; Jason R. Villarreal (SAMOS, 2009)

Boosting XML Filtering with a Scalable FPGA-based Architecture - Abhishek Mitra; Marcos R. Vieira; Petko Bakalov; Walid A. Najjar; Vassilis J. Tsotras (CoRR, 2009)

Tunable and Energy Efficient Bus Encoding Techniques. - Dinesh C. Suresh; Banit Agrawal; Jun Yang 002; Walid A. Najjar (IEEE Trans. Computers, 2009)

Energy-efficient encoding techniques for off-chip data buses. - Dinesh C. Suresh; Banit Agrawal; Jun Yang 002; Walid A. Najjar (ACM Trans. Embed. Comput. Syst., 2009)

Designing Modular Hardware Accelerators in C with ROCCC 2.0. - Jason R. Villarreal; Adrian Park 002; Walid A. Najjar; Robert J. Halstead (FCCM, 2010)

Exploration of Short Reads Genome Mapping in Hardware. - Edward Fernandez; Walid A. Najjar; Elena Yavorska Harris; Stefano Lonardi (FPL, 2010)

Accelerating XML Query Matching through Custom Stack Generation on FPGAs. - Roger Moussalli; Mariam Salloum; Walid A. Najjar; Vassilis J. Tsotras (HiPEAC, 2010)

Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs. - Doruk Sart; Abdullah Mueen; Walid A. Najjar; Eamonn J. Keogh; Vit Niennattrakul (ICDM, 2010)

Impact of high-level transformations within the ROCCC framework. - Betul Buyukkurt; John Cortes; Jason R. Villarreal; Walid A. Najjar (ACM Trans. Archit. Code Optim., 2010)

String Matching in Hardware Using the FM-Index. - Edward Fernandez; Walid A. Najjar; Stefano Lonardi (FCCM, 2011)

Massively parallel XML twig filtering using dynamic programming on FPGAs. - Roger Moussalli; Mariam Salloum; Walid A. Najjar; Vassilis J. Tsotras (ICDE, 2011)

Exploring irregular memory accesses on FPGAs. - Robert J. Halstead; Jason R. Villarreal; Walid A. Najjar (IA3@SC, 2011)

Efficient XML Path Filtering Using GPUs. - Roger Moussalli; Robert J. Halstead; Mariam Salloum; Walid A. Najjar; Vassilis J. Tsotras (ADMS@VLDB, 2011)

Multithreaded FPGA acceleration of DNA sequence mapping. - Edward Fernandez; Walid A. Najjar; Stefano Lonardi; Jason R. Villarreal (HPEC, 2012)

Efficient near-duplicate document detection using FPGAs. - Xi Luo; Walid A. Najjar; Vagelis Hristidis (IEEE BigData, 2013)

Compiled multithreaded data paths on FPGAs for dynamic workloads. - Robert J. Halstead; Walid A. Najjar (CASES, 2013)

FPGA code accelerators - the compiler perspective. - Walid A. Najjar; Jason R. Villarreal (DAC, 2013)

A High Throughput No-Stall Golomb-Rice Hardware Decoder. - Roger Moussalli; Walid A. Najjar; Xi Luo; Amna Khan (FCCM, 2013)

Stream-Mode FPGA Acceleration of Complex Pattern Trajectory Querying. - Roger Moussalli; Marcos R. Vieira; Walid A. Najjar; Vassilis J. Tsotras (SSTD, 2013)

High-Performance XML Twig Filtering using GPUs. - Ildar Absalyamov; Roger Moussalli; Vassilis J. Tsotras; Walid A. Najjar (ADMS@VLDB, 2013)

High-Throughput Fixed-Point Object Detection on FPGAs. - Xiaoyin Ma; Walid A. Najjar; Amit K. Roy-Chowdhury (FCCM, 2014)

Compiling irregular applications for reconfigurable systems. - Robert J. Halstead; Jason R. Villarreal; Walid A. Najjar (Int. J. High Perform. Comput. Netw., 2014)

Reconfigurable Computing. - Walid A. Najjar; Paolo Ienne (IEEE Micro, 2014)

A study on parallelizing XML path filtering using accelerators. - Roger Moussalli; Mariam Salloum; Robert J. Halstead; Walid A. Najjar; Vassilis J. Tsotras (ACM Trans. Embed. Comput. Syst., 2014)

FPGA-based Multithreading for In-Memory Hash Joins. - Robert J. Halstead; Ildar Absalyamov; Walid A. Najjar; Vassilis J. Tsotras (CIDR, 2015)

CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs. - Skyler Windh; Prerna Budhkar; Walid A. Najjar (ICCAD, 2015)

High performance FPGA and GPU complex pattern matching over spatio-temporal streams. - Roger Moussalli; Ildar Absalyamov; Marcos R. Vieira; Walid A. Najjar; Vassilis J. Tsotras (GeoInformatica, 2015)

High-Level Language Tools for Reconfigurable Computing. - Skyler Windh; Xiaoyin Ma; Robert J. Halstead; Prerna Budhkar; Zabdiel Luna; Omar Hussaini; Walid A. Najjar (Proc. IEEE, 2015)

FHAST: FPGA-Based Acceleration of Bowtie in Hardware. - Edward B. Fernandez; Jason R. Villarreal; Stefano Lonardi; Walid A. Najjar (IEEE ACM Trans. Comput. Biol. Bioinform., 2015)

Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs. - Xiaoyin Ma; Walid A. Najjar; Amit K. Roy-Chowdhury (IEEE Trans. Circuits Syst. Video Technol., 2015)

ROCCC 2.0. - Walid A. Najjar; Jason R. Villarreal; Robert J. Halstead (FPGAs for Software Programmers, 2016)

FPGA-accelerated group-by aggregation using synchronizing caches. - Ildar Absalyamov; Prerna Budhkar; Skyler Windh; Robert J. Halstead; Walid A. Najjar; Vassilis J. Tsotras (DaMoN, 2016)

Preface. - Paolo Ienne; Walid A. Najjar; Jason Helge Anderson; Philip Brisk; Walter Stechele (FPL, 2016)

Optimizing hardware design for Human Action Recognition. - Xiaoyin Ma; Jose M. Rodriguez Borbon; Walid A. Najjar; Amit K. Roy-Chowdhury (FPL, 2016)

PDES-A: a Parallel Discrete Event Simulation Accelerator for FPGAs. - Shafiur Rahman; Nael B. Abu-Ghazaleh; Walid A. Najjar (SIGSIM-PADS, 2017)

Massively parallel skyline computation for processing-in-memory architectures. - Vasileios Zois; Divya Gupta; Vassilis J. Tsotras; Walid A. Najjar; Jean-François Roy (PACT, 2018)

GPU Accelerated Top-K Selection With Efficient Early Stopping. - Vasileios Zois; Vassilis J. Tsotras; Walid A. Najjar (ADMS@VLDB, 2019)

Efficient Main-Memory Top-K Selection For Multicore Architectures. - Vasileios Zois; Vassilis J. Tsotras; Walid A. Najjar (Proc. VLDB Endow., 2019)

Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads. - Prerna Budhkar; Ildar Absalyamov; Vasileios Zois; Skyler Windh; Walid A. Najjar; Vassilis J. Tsotras (ACM Trans. Archit. Code Optim., 2019)

PDES-A: Accelerators for Parallel Discrete Event Simulation Implemented on FPGAs. - Shafiur Rahman; Nael B. Abu-Ghazaleh; Walid A. Najjar (ACM Trans. Model. Comput. Simul., 2019)

High-Performance Parallel Radix Sort on FPGA. - Bashar Romanous; Mohammadreza Rezvani; Junjie Huang; Daniel Wong 001; Evangelos E. Papalexakis; Vassilis J. Tsotras; Walid A. Najjar (FCCM, 2020)

Heterogeneous Acceleration of HAR Applications. - Jose M. Rodriguez Borbon; Xiaoyin Ma; Amit K. Roy-Chowdhury; Walid A. Najjar (IEEE Trans. Circuits Syst. Video Technol., 2020)

Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs. - Jose M. Rodriguez Borbon; Junjie Huang; Bryan M. Wong; Walid A. Najjar (ACM Trans. Archit. Code Optim., 2021)

Efficient local locking for massively multithreaded in-memory hash-based operators. - Bashar Romanous; Skyler Windh; Ildar Absalyamov; Prerna Budhkar; Robert J. Halstead; Walid A. Najjar; Vassilis J. Tsotras (VLDB J., 2021)

First Twenty Years of the International Symposium on Applied Reconfigurable Computing (ARC): A Selection of Papers. - João M. P. Cardoso; Walid A. Najjar (ARC, 2025)