Submicron Scaling of Indium Phosphide/indium Gallium Arsenide Heterojunction Bipolar Transistors Toward Terahertz Bandwidths - Walid M. Hafez (2005)

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; Ian Post; et al. (ISSCC, 2007)

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; et al. (IEEE J. Solid State Circuits, 2008)

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. - Chia-Hong Jan; F. Al-amoody; H.-Y. Chang; T. Chang; Y.-W. Chen; N. Dias; Walid M. Hafez; Doug B. Ingerly; M. Jang; Eric Karl; S. K.-Y. Shi; K. Komeyli; et al. (VLSIC, 2015)

Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing. - Bernhard Sell; S. An; J. Armstrong; D. Bahr; B. Bains; Rohan Bambery; K. Bang; D. Basu; S. Bendapudi; D. Bergstrom; R. Bhandavat; S. Bhowmick; et al. (VLSI Technology and Circuits, 2022)

Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing. - Walid M. Hafez; P. Agnihotri; M. Asoro; M. Aykol; B. Bains; Rohan Bambery; M. Bapna; A. Barik; A. Chatterjee; P. C. Chiu; T. Chu; C. Firby; et al. (VLSI Technology and Circuits, 2023)

E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology. - M. Shamanna; E. Abuayob; G. Aenuganti; C. Alvares; J. Antony; A. Bahudhanam; A. Chandran; P. Chew; A. Chatterjee; B. Chauhan; N. Dandeti; J. Desai; et al. (VLSI Technology and Circuits, 2023)

An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications. - Walid M. Hafez; D. Abanulo; M. Abdelkader; S. An; C. Auth; D. Bahr; V. Balakrishnan; Rohan Bambery; M. Beck; M. Bhargava; S. Bhowmick; J. Biggs-houck; et al. (VLSI Technology and Circuits, 2024)