A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring. - Walker J. Turner; Rizwan Bashirullah (VLSIC, 2014)

A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring. - Walker J. Turner; Rizwan Bashirullah (IEEE J. Solid State Circuits, 2016)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. - Haoxing Ren; George F. Kokai; Walker J. Turner; Ting-Sheng Ku (DAC, 2020)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop. - Nandish Mehta; Stephen G. Tell; Walker J. Turner; Lamar Tatro; Giant Goh; C. Thomas Gray (A-SSCC, 2021)

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. - Mingjie Liu; Walker J. Turner; George F. Kokai; Brucek Khailany; David Z. Pan; Haoxing Ren (DATE, 2021)

Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories. - Hao Chen 059; Walker J. Turner; David Z. Pan; Haoxing Ren (DATE, 2022)

TAG: Learning Circuit Spatial Embedding from Layouts. - Keren Zhu 001; Hao Chen 059; Walker J. Turner; George F. Kokai; Po-Hsuan Wei; David Z. Pan; Haoxing Ren (ICCAD, 2022)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. - Hao Chen 059; Walker J. Turner; Sanquan Song; Keren Zhu 001; George F. Kokai; Brian Zimmer; C. Thomas Gray; Brucek Khailany; David Z. Pan; Haoxing Ren (ISPD, 2022)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. - Yoshinori Nishi; John W. Poulton; Xi Chen 033; Sanquan Song; Brian Zimmer; Walker J. Turner; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (VLSI Technology and Circuits, 2022)

An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop. - Nandish Mehta; Stephen G. Tell; Walker J. Turner; Lamar Tatro; Jih Ren Goh; C. Thomas Gray (IEEE J. Solid State Circuits, 2022)

Reinforcement Learning Guided Detailed Routing for Custom Circuits. - Hao Chen 059; Kai-Chieh Hsu; Walker J. Turner; Po-Hsuan Wei; Keren Zhu 001; David Z. Pan; Haoxing Ren (ISPD, 2023)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2023)

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. - Walker J. Turner; John W. Poulton; Yoshinori Nishi; Xi Chen 033; Brian Zimmer; Sanquan Song; John M. Wilson 002; William J. Dally; C. Thomas Gray (CICC, 2024)

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2024)

ChipVQA: Benchmarking Visual Language Models for Chip Design. - Haoyu Yang; Qijing Huang 001; Nathaniel Ross Pinckney; Walker J. Turner; Wenfei Zhou; Yanqing Zhang 002; Chia-Tung Ho; Chen-Chia Chang; Haoxing Ren (DATE, 2025)