Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen. - B. Lauerbach; Walter Anheier (DAGM-Symposium, 1993)

A New Strategy for Test Pattern Generation in Sequential Circuits. - Beom-Ik Cheon; Walter Anheier; Rainer Laur (ISCAS, 1994)

Segmentation of Scanned Maps in Uniform Color Spaces. - Bernd Lauterbach; Walter Anheier (MVA, 1994)

An image analysis system for automatic data acquisition from colored scanned maps. - Norbert Ebi; Bernd Lauterbach; Walter Anheier (Mach. Vis. Appl., 1994)

Distributed automatic test pattern generation with a parallel FAN algorithm. - Stefan Radtke; Jens Bargfrede; Walter Anheier (ICCD, 1995)

Processor Elements for the Standard Cell Implementation of Residue Number Systems. - Ansgar Drolshagen; Heiko Henkelmann; Walter Anheier (ASAP, 1997)

A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. - Ansgar Drolshagen; Walter Anheier; C. Chandra Sekhar (VLSI Design, 1998)

Implementation of sign detection in RNS using mixed radix representation. - Heiko Henkelmann; Walter Anheier (ICECS, 1999)

Efficient VLSI implementation of modern symmetric block ciphers. - A. Schubert; Walter Anheier (ICECS, 1999)

Effiziente Methoden zum Zahlenvergleich und zur Vorzeichenerkennung in Restklassensystemen. - Heiko Henkelmann; C. Bruennlein; Walter Anheier (MBMV, 1999)

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. - Frank Poehl; Walter Anheier (J. Electron. Test., 1999)

On Random Pattern Testability of Cryptographic VLSI Cores. - A. Schubert; Walter Anheier (J. Electron. Test., 2000)

Investigations of on-line/off-line tests for sensors. - Michael Fischell; Walter Anheier (ICECS, 2001)

Non-robust delay test pattern generation based on stuck-at TPG. - Volker Meyer; Walter Anheier; Arne Sticht (ICECS, 2001)

Integer division in residue number system. - Badreddine Rejeb; Heiko Henkelmann; Walter Anheier (ICECS, 2001)

Backpropagation based training algorithm for Takagi-Sugeno type MIMO neuro-fuzzy network to forecast electrical load time series. - Ajoy Kumar Palit; Gerhard Doeding; Walter Anheier; Dobrivoje Popovic (FUZZ-IEEE, 2002)

Non-robust delay test pattern enhancement. - Volker Meyer; Walter Anheier; Arne Sticht (ICECS, 2002)

Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. - Ajoy Kumar Palit; Volker Meyer; Walter Anheier; Jürgen Schlöffel (DFT, 2004)

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. - Ajoy Kumar Palit; Lei Wu; Kishore K. Duganapalli; Walter Anheier; Jürgen Schlöffel (Asian Test Symposium, 2005)

ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. - Ajoy Kumar Palit; Volker Meyer; Walter Anheier; Jürgen Schlöffel (VLSI Design, 2005)

Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. - Ajoy Kumar Palit; Kishore K. Duganapalli; Walter Anheier (DFT, 2006)

Reduction of Crosstalk Pessimism using Tendency Graph Approach. - Murthy Palla; Klaus Koch; Jens Bargfrede; Manfred Glesner; Walter Anheier (ICCD, 2006)

Vergleich und Optimierung von Algorithmen zur Modulo-Multiplikation auf Smartcards. - Sascha Kneip; Walter Anheier (MBMV, 2006)

Modeling of Crosstalk Fault in Defective Interconnects. - Ajoy Kumar Palit; Kishore K. Duganapalli; Walter Anheier (PATMOS, 2006)

XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. - Ajoy Kumar Palit; Kishore K. Duganapalli; Walter Anheier (DDECS, 2007)

Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. - Murthy Palla; Jens Bargfrede; Klaus Koch; Walter Anheier; Rolf Drechsler (ISQED, 2008)

Crosstalk fault modeling in defective pair of interconnects. - Ajoy Kumar Palit; Kishore K. Duganapalli; Walter Anheier (Integr., 2008)

Timing Arc based logic analysis for false noise reduction. - Murthy Palla; Jens Bargfrede; Stephan Eggersglüß; Walter Anheier; Rolf Drechsler (ICCAD, 2009)

Electrical Load Forecasting Using a Neural-Fuzzy Approach. - Ajoy Kumar Palit; Walter Anheier; Dobrivoje Popovic (Natural Intelligence for Scheduling, Planning and Packing Problems, 2009)

Efficient Training Algorithm for Neuro-Fuzzy Network and its Application to Nonlinear Sensor Characteristic Linearization. - Ajoy Kumar Palit; Walter Anheier (Intelligent Systems for Automated Learning and Adaptation, 2010)

Fault diagnosis of crosstalk induced glitches and delay faults. - Shehzad Hasan; Ajoy Kumar Palit; Walter Anheier (DDECS, 2010)

Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. - Shehzad Hasan; Ajoy Kumar Palit; Walter Anheier (VLSI Design, 2010)

TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. - Kishore K. Duganapalli; Ajoy Kumar Palit; Walter Anheier (DDECS, 2015)

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim. - Kishore K. Duganapalli; Ajoy Kumar Palit; Walter Anheier (J. Circuits Syst. Comput., 2016)