Basic Design of a Josephson Technology Cache Memory. - S. M. Faris; Walter H. Henkels; E. A. Valsamakis; H. H. Zappe (IBM J. Res. Dev., 1980)

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. - Nicky Chau-Chun Lu; Gary B. Bronner; Koji Kitamura; Roy E. Scheuerlein; Walter H. Henkels; Sang H. Dhong; Yasunao Katayama; Toshiaki Kirihata; Hideto Niijima; Robert L. Franch; Wei Wang; Motoo Nishiwaki; et al. (IEEE J. Solid State Circuits, 1989)

Internal node probing of a DRAM with a low-temperature e-beam tester. - Keith A. Jenkins; Walter H. Henkels (IEEE J. Solid State Circuits, 1991)

A 4-Mb low-temperature DRAM. - Walter H. Henkels; Duen-Shun Wen; Rick L. Mohler; Robert L. Franch; Thomas J. Bucelot; Christopher W. Long; John A. Bracchitta; W. J. Cote; Gary B. Bronner; Yuan Taur; Robert H. Dennard (IEEE J. Solid State Circuits, 1991)

Large-signal 2T, 1C DRAM cell: signal and layout analysis. - Walter H. Henkels; Wei Hwang (IEEE J. Solid State Circuits, 1994)

A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. - Wei Hwang; Rajiv V. Joshi; Walter H. Henkels (ICCD, 1997)

A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. - Wei Hwang; Rajiv V. Joshi; Walter H. Henkels (IEEE J. Solid State Circuits, 1999)