A standard cell characterization flow for non-standard voltage supplies. - Matheus Gibiluka; Matheus Trevisan Moreira; Walter Lau Neto; Ney Laert Vilar Calazans (SBCCI, 2016)

Sleep convention logic isochronic fork: an analysis. - Ricardo A. Guazzelli; Matheus T. Moreira; Walter Lau Neto; Ney Laert Vilar Calazans (SBCCI, 2017)

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; André Inácio Reis; Renato P. Ribas (SBCCI, 2018)

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. - Walter Lau Neto; Max Austin; Scott Temple; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (ICCAD, 2019)

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. - Walter Lau Neto; Xifan Tang; Max Austin; Luca G. Amarù; Pierre-Emmanuel Gaillardon (ISVLSI, 2019)

A Scalable Mixed Synthesis Framework for Heterogeneous Networks. - Max Austin; Scott Temple; Walter Lau Neto; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (DATE, 2020)

Exact Benchmark Circuits for Logic Synthesis. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; Pierre-Emmanuel Gaillardon; André Inácio Reis; Renato Perez Ribas (IEEE Des. Test, 2020)

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. - Walter Lau Neto; Matheus Trevisan Moreira; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (ASP-DAC, 2021)

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. - Walter Lau Neto; Matheus T. Moreira; Yingjie Li; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (DAC, 2021)

Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. - Scott Temple; Walter Lau Neto; Ashton Snelgrove; Xifan Tang; Pierre-Emmanuel Gaillardon (DAC, 2021)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

Improving LUT-based optimization for ASICs. - Walter Lau Neto; Luca G. Amarù; Vinicius Possani; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon (DAC, 2022)

End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit. - Walter Lau Neto; Yingjie Li; Pierre-Emmanuel Gaillardon; Cunxi Yu (CoRR, 2022)

A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. - Gabriel Ammes; Walter Lau Neto; Paulo F. Butzen; Pierre-Emmanuel Gaillardon; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit. - Walter Lau Neto; Yingjie Li; Pierre-Emmanuel Gaillardon; Cunxi Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Scalable Sequential Optimization Under Observability Don't Cares. - Dewmini Sudara Marakkalage; Eleonora Testa; Walter Lau Neto; Alan Mishchenko; Giovanni De Micheli; Luca G. Amarù (DATE, 2024)