Adder-based digital signal processor architecture for 80 NS cycle time. - Alois Rainer; Walter Ulbrich; Lajos Gazsi (ICASSP, 1984)

MOS-VLSI pipelined digital filters for video applications. - Walter Ulbrich; Tobias G. Noll; B. Zehner (ICASSP, 1984)

FIR Lowpass filter for signal decimation with 15 MHz clock frequency. - A. Huber; Erik De Man; E. Schiller; Walter Ulbrich (ICASSP, 1986)

A fast adder-based multiplication unit for customised digital signal processors. - Luc de Vos; Rajeev Jain; Hugo De Man; Walter Ulbrich (ICASSP, 1986)