Mechanism for return stack and branch history corrections under misprediction in deep pipeline design. - Guan-Ying Chiu; Hui-Chin Yang; Walter Yuan-Hwa Li; Chung-Ping Chung (ACSAC, 2008)

Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity. - Walter Yuan-Hwa Li; Chin-Ling Huang; Chung-Ping Chung (ICPP, 2011)