Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. - Juinn-Dar Huang; Chia-I Chen; Yen-Ting Lin; Wan-Ling Hsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. - Juinn-Dar Huang; Chia-I Chen; Wan-Ling Hsu; Yen-Ting Lin; Jing-Yang Jou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Enhancing healthcare services and brand engagement through social media marketing: Integration of Kotler's 5A framework with IDEA process. - Chih-Lung Hung; Jen-Her Wu; Pei-Yu Chen; Xiaoyu Xu; Wan-Ling Hsu; Li-Min Lin; Ming-Che Hsieh (Inf. Process. Manag., 2023)