Testable Design and Testing of MCMs Based on Multifrequency Scan. - Wang-Dauh Tseng; Kuochen Wang (Asian Test Symposium, 1996)

Fuzzy-based circuit partitioning in built-in current testing. - Wang-Dauh Tseng; Kuochen Wang (ASP-DAC, 1997)

Fuzzy-based CMOS circuit partitioning in built-in current testing. - Wang-Dauh Tseng; Kuochen Wang (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Printed circuit board routing and package layout codesign. - Shuenn-Shi Chen; Wang-Dauh Tseng; Jin-Tai Yan; Sao-Jie Chen (APCCAS (1), 2002)

A novel dynamic fault restoration mechanism using cluster allocation approach in WDM mesh networks. - I-Shyan Hwang; Meng-Yuan Tu; Wang-Dauh Tseng; Zen-Der Shyu (Comput. Commun., 2006)

Reduction of Power Dissipation during Scan Testing by Test Vector Ordering. - Wang-Dauh Tseng; Lung-Jen Lee (MTV, 2007)

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing. - Wang-Dauh Tseng (J. Electron. Test., 2007)

A novel dynamic Multiple Ring-based Local Restoration for point-to-multipoint multicast traffic in WDM mesh networks. - I-Shyan Hwang; Ren-Yuan Cheng; Wang-Dauh Tseng (Photonic Netw. Commun., 2007)

Power Reduction during Scan Testing Based on Multiple Capture Technique. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin (IEICE Trans. Electron., 2008)

A Multi-dimensional Pattern Run-Length Method for Test Data Compression. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin; Chen-Lun Lee (Asian Test Symposium, 2009)

Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin; Chi-Wei Yu (Asian Test Symposium, 2009)

Test Data Compression Using Multi-dimensional Pattern Run-length Codes. - Wang-Dauh Tseng; Lung-Jen Lee (J. Electron. Test., 2010)

Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction. - Wang-Dauh Tseng; Lung-Jen Lee; Rung-Bin Lin (IET Comput. Digit. Tech., 2010)

Deterministic ATPG for Low Capture Power Testing. - Lung-Jen Lee; Chia-Cheng He; Wang-Dauh Tseng (MTV, 2012)

Two-Way Multicasting for Test Data Compression. - Lung-Jen Lee; Wang-Dauh Tseng; Wei-Shun Chen (MTV, 2012)

Dual-LFSR Reseeding for Low Power Testing. - Lung-Jen Lee; Wang-Dauh Tseng; Wen-Ting Yang (MTV, 2012)

$2^{n}$ Pattern Run-Length for Test Data Compression. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin; Cheng-Ho Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Bipolar Dual-LFSR Reseeding for Low-Power Testing. - Jen-Cheng Ying; Wang-Dauh Tseng; Wen-Jiin Tsai (DSC, 2018)

Asymmetry dual-LFSR reseeding for low power BIST. - Jen-Cheng Ying; Wang-Dauh Tseng; Wen-Jiin Tsai (Integr., 2018)

Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction. - Jen-Cheng Ying; Wang-Dauh Tseng; Wen-Jiin Tsai (J. Inf. Sci. Eng., 2019)

A Cascaded Multicasting Architecture for Test Data Compression. - Wang-Dauh Tseng (J. Electron. Test., 2021)