CodSim – A Combined Delay Fault Simulator. - Wangqi Qiu; Xiang Lu; Zhuo Li 001; D. M. H. Walker; Weiping Shi (DFT, 2003)

An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. - Wangqi Qiu; D. M. H. Walker (ITC, 2003)

Testing the Path Delay Faults of ISCAS85 Circuit c6288. - Wangqi Qiu; D. M. H. Walker (MTV, 2003)

A Circuit Level Fault Model for Resistive Opens and Bridges. - Zhuo Li 001; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (VTS, 2003)

A circuit level fault model for resistive bridges. - Zhuo Li 001; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (ACM Trans. Design Autom. Electr. Syst., 2003)

PARADE: PARAmetric Delay Evaluation under Process Variation. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (ISQED, 2004)

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. - Wangqi Qiu; Jing Wang 006; D. M. H. Walker; Divya Reddy; Zhuo Li 001; Weiping Shi; Hari Balachandran (ITC, 2004)

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (MTV, 2004)

Minimum moment Steiner trees. - Wangqi Qiu; Weiping Shi (SODA, 2004)

A Statistical Fault Coverage Metric for Realistic Path Delay Faults. - Wangqi Qiu; Xiang Lu; Jing Wang 006; Zhuo Li 001; D. M. H. Walker; Weiping Shi (VTS, 2004)

A vector-based approach for power supply noise analysis in test compaction. - Jing Wang 006; Ziding Yue; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (ITC, 2005)

Static Compaction of Delay Tests Considering Power Supply Noise. - Jing Wang 006; Xiang Lu; Wangqi Qiu; Ziding Yue; Steve Fancler; Weiping Shi; D. M. H. Walker (VTS, 2005)

Longest-path selection for delay test under process variation. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Comparison of Delay Tests on Silicon. - Wangqi Qiu; D. M. H. Walker; Neil Simpson; Divya Reddy; Anthony Moore (ITC, 2006)

Fault simulation and test generation for small delay faults. - Wangqi Qiu (2007)

Macro Model of Advanced Devices for Parasitic Extraction. - Yuhan Zhou; Yong Zhang; Vivek Sarin; Wangqi Qiu; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)