Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. - Shihui Yin; Jae-sun Seo; Yulhwa Kim; Xu Han; Hugh J. Barnaby; Shimeng Yu; Yandong Luo; Wangxin He; Xiaoyu Sun 001; Jae-Joon Kim (IEEE Micro, 2019)

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. - Wangxin He; Wonbo Shim; Shihui Yin; Xiaoyu Sun 001; Deliang Fan; Shimeng Yu; Jae-sun Seo (IRPS, 2021)

Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks. - Vinay Joshi; Wangxin He; Jae-sun Seo; Bipin Rajendran (ISCAS, 2021)

PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. - Wangxin He; Jian Meng; Sujan Kumar Gonugondla; Shimeng Yu; Naresh R. Shanbhag; Jae-sun Seo (DATE, 2023)

A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment. - Fan Zhang 069; Wangxin He; Injune Yeo; Maximilian Liehr; Nathaniel C. Cady; Yu Cao 001; Jae-Sun Seo; Deliang Fan (ESSCIRC, 2023)

A 65-nm RRAM Compute-in-Memory Macro for Genome Processing. - Fan Zhang 069; Amitesh Sridharan; Wangxin He; Injune Yeo; Maximilian Liehr; Wei Zhang 076; Nathaniel C. Cady; Yu Cao 001; Jae-Sun Seo; Deliang Fan (IEEE J. Solid State Circuits, 2024)