A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process. - Joohwan Kim; Junyoung Park; Jindo Byun; Changkyu Seol; Chang Soo Yoon; EunSeok Shin; Hyunyoon Cho; Youngdo Um; Sucheol Lee; Hyungmin Jin; Kwangseob Shin; Hyunsub Norbert Rie; et al. (CICC, 2022)

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)